EP20K1000CF672C8N vs EP20K1000CF672I8 Comparison
Detailed side-by-side comparison of EP20K1000CF672C8N by Intel and EP20K1000CF672I8 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K1000CF672C8N | EP20K1000CF672I8 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $178.40 | $165.00 |
| Device Family | APEX 20KC | β |
| Device Type | FPGA (Field Programmable Gate Array) | β |
| Logic Elements / Cells | 38,400 | 38,400 |
| Equivalent Gate Count | 1,000,000 gates | β |
| Embedded Memory (bits) | 327,680 | β |
| Number of I/Os | 488 to 508 | β |
| Number of Pins / Balls | 672 | β |
| Package | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch | 672-pin FC-FBGA (FineLine BGA) |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Operating Temperature | 0Β°C to 85Β°C (Commercial) | -40 Β°C to +85 Β°C (industrial, I suffix) |
| Supply Voltage (Vccint) | 1.8 V | β |
| Process Technology | 0.15 Β΅m all-layer copper | 0.15 Β΅m CMOS |
| Internal Operating Frequency (max) | 301.21 MHz | β |
| Propagation Delay (typ.) | 1.6 ns to 1.79 ns | β |
| Architecture | MultiCore (LUT + embedded memory + product-term) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | β |
| Pin-to-Pin Compatibility | APEX 20KE family (same 672-ball BGA) | β |
| Family | β | APEX 20KC |
| Manufacturer | β | Intel (formerly Altera) |
| System Gates | β | 1,000,000 |
| Ball Pitch | β | 1.00 mm |
| Core Supply Voltage | β | 1.71 V to 1.89 V (1.8 V nominal) |
| User I/O Count | β | 508 |
| Dedicated Inputs | β | 4 |
| Internal Frequency (max) | β | 301.21 MHz |
| Pin-to-Pin Logic Delay | β | 8 ns |
| Memory Type | β | SRAM-based (volatile) |
| Embedded Memory | β | Embedded Array Blocks (EABs) for dual-port RAM / FIFO |
| PLL Count | β | 4 |
| I/O Standards | β | LVTTL, LVCMOS, PCI, SSTL, HSTL |
| MSL Level | β | [DATA_NEEDED: MSL level] |