EP20K1000EBC652-2X vs EP20K1000EFI672-2X Comparison
Detailed side-by-side comparison of EP20K1000EBC652-2X by Altera and EP20K1000EFI672-2X by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K1000EBC652-2X
EP20K1000EBC652-2X - 1M Gate APEX-20KE FPGA, 488 I/O, 652-BGA | Altera (Intel)
EP20K1000EBC652-2X NrndIntel
EP20K1000EFI672-2X
EP20K1000EFI672-2X - 1M Gate APEX-20KE FPGA 672-BGA | Intel
EP20K1000EFI672-2X NrndSpecification Comparison
| Parameter | EP20K1000EBC652-2X | EP20K1000EFI672-2X |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $99.00 | $305.00 |
| Family | APEX-20KE | APEX-20KE |
| Device Logic Elements | 38,400 | β |
| Typical Gates | 1,000,000 system gates | β |
| Embedded Memory Bits | 327,680 bits | β |
| User I/O Pins | 488 | β |
| Maximum User I/O | 488 | β |
| Propagation Delay | 1.6 ns | 1.6 ns |
| Internal Maximum Frequency | 350 MHz | β |
| Logic Blocks / Macros | 2,560 macros | β |
| PLLs | 4 | β |
| Core Voltage | 1.8 V | 1.8 V |
| Process Technology | 0.22 Β΅m (some sources 0.15 Β΅m) all-layer copper-metal CMOS | 0.15 micron all-layer copper-metal |
| Package | 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) | 0C to +85C |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Altera configuration | β |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Device Type | β | SPLD / FPGA |
| Logic Elements / Cells | β | 38400 |
| System Gates | β | 1,000,000 |
| Number of Macros | β | 2560 |
| Embedded Memory (Bits) | β | 327680 |
| User I/Os | β | 508 |
| Number of I/O Banks | β | [DATA_NEEDED: I/O banks] |
| I/O Voltage Support | β | 1.8 V / 2.5 V / 3.3 V |
| Package Type | β | 672-BBGA (FineLine BGA, 45 x 45 mm, 1.27 mm pitch) |
| JTAG Support | β | IEEE 1149.1 boundary-scan |
| PLL Count | β | 4 |
| Speed Grade | β | -2X |
| MSL Level | β | [DATA_NEEDED: MSL level] |