EP20K1000EFI672-2X - 1M Gate APEX-20KE FPGA 672-BGA | Intel
MPN: EP20K1000EFI672-2X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $425 | $425.00 |
| 10 | $395 | $3,950.00 |
| 100 | $365 | $36,500.00 |
| 500 | $335 | $167,500.00 |
| 1,000 | $305 | $305,000.00 |
EP20K1000EFI672-2X Overview
An FPGA (Field Programmable Gate Array) is a semiconductor integrated circuit built around an array of configurable logic blocks (CLBs), embedded memory, embedded multipliers or DSP blocks, and a programmable interconnect fabric. FPGAs occupy the high-density tier of programmable logic devices, sitting above CPLDs and below ASICs in the taxonomy of digital logic ICs: programmable logic device (PLD) -> CPLD -> FPGA -> ASIC. APEX-20KE devices specifically combine look-up-table based logic with embedded array blocks (EABs) that can act as RAM, ROM, or FIFO memory.
Key features include 508 user I/Os, 2560 macrocells, 1.6 ns propagation delay, multi-volt I/O support (1.8V, 2.5V, 3.3V) on a 1.8V core supply, embedded CAM and RAM, four phase-locked loops for clock management, and JTAG-based IEEE 1149.1 boundary-scan testing. The device integrates LVDS, LVTTL, LVPECL, and PCI-compatible I/O standards, enabling direct interfacing with high-speed peripherals and backplanes.
The EP20K1000EFI672-2X uses a symmetric LUT-based architecture with embedded system blocks (ESBs) that can be configured individually as either logic or memory. Its high gate count, 488 pins of user I/O, and embedded multipliers make it suited for DSP pipelines, custom processor implementations, and high-bandwidth glue logic. Compared with smaller APEX-20KE siblings, this 1M-gate device is the densest in the family.
Typical applications include telecom line cards, network routers, custom DSP accelerators, high-speed image processing pipelines, and industrial control processors. The wide I/O count also makes it usable as a multi-protocol bridge or as a system-on-chip integrator in legacy 32-bit and 16-bit processor designs.
When designing with this part, plan power sequencing carefully because the 1.8V core and multi-voltage I/O rails ramp independently; use the JTAG port for in-system programming and rely on the four PLLs to derive multiple clock domains without external clock buffers.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that supplement the manufacturer datasheet and help engineers shorten the selection cycle.
Drop-in alternatives for EP20K1000EFI672-2X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K1000EFI672-2X (same form factor and footprint) — differing in Operating Temperature, Package, Process Technology, Mounting Type, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K1000EBI652-2
✅ Drop-In✓ In Stock
$105 / Unit
View Datasheet →EP20K1000EBC652-2X
✅ Drop-In✓ In Stock
$99 / Unit
View Datasheet →EP20K1000CB652I9
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EP20K1000CB652C7NJ
✅ Drop-In✓ In Stock
$175 / Unit
View Datasheet →EP20K1000EFI672-2X Maximum Ratings & Electrical Characteristics
| Family | APEX-20KE |
| Device Type | SPLD / FPGA |
| Logic Elements / Cells | 38400 |
| System Gates | 1,000,000 |
| Number of Macros | 2560 |
| Embedded Memory (Bits) | 327680 |
| User I/Os | 508 |
| Propagation Delay | 1.6 ns |
| Core Voltage | 1.8 V |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature | 0C to +85C |
| Package Type | 672-BBGA (FineLine BGA, 45 x 45 mm, 1.27 mm pitch) |
| Mounting Type | Surface Mount |
| Process Technology | 0.15 micron all-layer copper-metal |
| JTAG Support | IEEE 1149.1 boundary-scan |
| PLL Count | 4 |
| Speed Grade | -2X |
EP20K1000EFI672-2X 672-bbga (fineline bga, 45 x 45 mm, 1.27 mm pitch) Pin Configuration Guide
Pin configuration for EP20K1000EFI672-2X (672-bbga (fineline bga, 45 x 45 mm, 1.27 mm pitch) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K1000EFI672-2X.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K1000EFI672-2X is suitable for 6 applications: Telecom Line Card Interface Aggregation, Custom DSP Accelerator Pipeline, High-Speed Industrial Control Processor, Multi-Protocol Bridge and Bus Converter, Image Processing Front-End, Legacy 32-bit Processor Integration Platform.
Telecom Line Card Interface Aggregation
The EP20K1000EFI672-2X is well suited to telecom line cards because its 508 user I/Os allow direct aggregation of multiple T1/E1, E3, and low-order SONET/SDH framers without external glue logic. The 1,000,000 system gates provide ample headroom for HDLC controllers, framer back-pressure FIFOs, and protocol-conversion state machines. Its 1.8V core plus multi-voltage I/O lets it bridge 3.3V framer ASICs and 2.5V network processors on the same board, reducing BOM count. The four on-chip PLLs generate independent clocks for each framer, replacing external clock buffers.
Recommended
Custom DSP Accelerator Pipeline
With 38,400 logic elements plus 327,680 embedded memory bits (ESBs configurable as RAM/ROM/FIFO), the EP20K1000EFI672-2X supports wide parallel DSP pipelines such as FFT engines, Viterbi decoders, and multi-channel filters. The 1.6 ns LUT delay at speed grade -2X lets designs hit 150-200 MHz Fmax in deeply pipelined DSP paths, suitable for baseband signal processing in software-defined radio and image processing applications. The ESB memory acts as coefficient and line buffers, eliminating external SRAM in many filter designs.
Recommended
High-Speed Industrial Control Processor
The 508 I/O count and PCI-compatible I/O standard support of the EP20K1000EFI672-2X make it a strong choice for custom industrial controllers that need to interface many sensors, motor drivers, and fieldbuses in a single device. The 1.8V core at 0.15 micron delivers modest power consumption, while the 0C to 85C commercial temperature range covers most factory-floor enclosures. JTAG boundary-scan simplifies board test for high-density BGA designs.
Recommended
Multi-Protocol Bridge and Bus Converter
Engineers building bridges between legacy peripheral buses (PCI, ISA, VME) and modern high-speed serial links (LVDS, RapidIO) often rely on the EP20K1000EFI672-2X. Its mix of LVTTL, LVDS, and PCI I/O standards lets it speak directly to bus transceivers without external level shifters. The 1M-gate capacity supports full protocol stacks with state machines, DMA engines, and on-chip FIFOs in a single device, replacing what would otherwise require an ASIC plus companion FPGA.
Recommended
Image Processing Front-End
The EP20K1000EFI672-2X with 38,400 logic cells and 327 kbit embedded RAM supports real-time image processing pipelines such as Bayer demosaic, color correction, and edge detection at resolutions up to 1080p at modest frame rates. Its 1.6 ns LUT delay allows pipelined pixel paths at 100+ MHz, and the LVDS I/O can directly interface CMOS image sensors with serialized outputs. ESB blocks implement line buffers, removing the need for external SRAM in many designs.
Recommended
Legacy 32-bit Processor Integration Platform
Engineers maintaining legacy Nios, 68k, or MIPS soft-core designs often use the EP20K1000EFI672-2X as the integration platform because it can host a 32-bit RISC CPU plus peripherals in a single FPGA. The 1M-gate capacity supports caches, MMUs, and interrupt controllers, while the 508 user I/Os expose the full external bus. JTAG-based debugging remains usable through Altera's Quartus II toolchain, which still supports APEX-20KE bitstream generation.
Recommended
Recommended Products Summary
Engineering reference data for EP20K1000EFI672-2X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K1000EBI652-2 | EP20K1000EBC652-2X | EP20K1000CB652I9 | EP20K1000CB652C7NJ |
|---|---|---|---|---|---|
| Package | 672-BBGA (45x45 mm) | 652-BGA (same family) | 652-BGA (same family) | 652-BGA (same family) | 652-BGA (same family) |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family | APEX-20KE | APEX-20KE | APEX-20KE | APEX-20K (not KE) | APEX-20K (not KE) |
| System Gates | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 |
| Speed Grade | -2X | -2 (slower by ~10%) | -2X (same) | -9 (much slower) | -7 (slower) |
| Operating Temperature | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C (industrial) | 0C to +85C |
| Embedded Memory (bits) | 327,680 | 327,680 | 327,680 | 327,680 | 327,680 |
Key Differentiators
- Highest gate density in APEX-20KE family (vs EP20K600EBI652-2X)
- Largest embedded memory in APEX-20KE family (vs EP20K600EBI652-2X)
- 508 user I/Os vs lower-pin APEX-20KE variants (vs EP20K400EBI452-2X)
Design Notes
Estimated: At 508 I/Os toggling at 100 MHz with 10 pF load, dynamic power is approximately 2.5-3.5 W. With a 672-BBGA package theta_JA of about 15-20 C/W (typical for 45x45 mm BGA on a 4-layer PCB), junction temperature can rise 40-70 C above ambient. Place thermal vias under the BGA and consider a heatsink for high-activity designs. The 0.15 micron process is more power-efficient than earlier APEX 20K devices, but full-gate utilization still requires thermal management.
The 672-BBGA at 1.27 mm pitch requires PCB escape routing on a 4-layer board with at least 6 mil trace/space. Use a dog-bone fanout for inner rows and via-in-pad for BGA corners. Maintain continuous ground planes under the BGA for both signal integrity and thermal dissipation. Multiple decoupling capacitors (0.1 uF and 10 uF) must be placed within 5 mm of the package for the 1.8V core rail and each I/O bank.
Do not assume the APEX-20KE is fully Quartus II compatible without verifying the device support file is installed - older MAX+PLUS II designs may require a Quartus import and recompile. The four PLLs have specific input clock and feedback divider constraints; consult the APEX-20KE datasheet PLL section before locking timing. The JTAG TRST pin must be tied low or driven properly; floating TRST can lock the device in JTAG mode unintentionally.
Compliance Information
Compliance data was not present in the verified web data. APEX-20KE family is a legacy 0.15 micron product; engineers should request RoHS/REACH compliance certificates from Intel directly.
