EP20K100EBC356-3N vs EP20K200EBC356-2 Comparison
Detailed side-by-side comparison of EP20K100EBC356-3N by Altera and EP20K200EBC356-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K100EBC356-3N | EP20K200EBC356-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.00 | $99.50 |
| Series | APEX-20KE | APEX 20KE |
| Family | APEX 20K | APEX 20K (APEX 20KE enhancement) |
| Logic Elements / Cells | 4160 | β |
| System Gates | 100,000 | β |
| Embedded Memory (bits) | 53,248 | β |
| Embedded System Blocks (ESBs) | 26 | β |
| Maximum User I/Os | 246 | β |
| Number of Pins | 356 | β |
| Package | 356-LBGA (Ball Grid Array) | β |
| Package Dimensions | 45 x 45 mm | β |
| Ball Pitch | 1.27 mm | β |
| Process Technology | 0.22 Β΅m CMOS | β |
| Core Supply Voltage | 1.8 V | β |
| Propagation Delay | 1.6 ns (speed grade -3N) | 2.5 ns |
| Maximum Internal Frequency | 250 MHz | β |
| Operating Temperature | 0 Β°C to +85 Β°C | 0 C to 85 C (commercial) |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Programmable Interface | JTAG (IEEE 1149.1) | β |
| I/O Standards Supported | LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+ | β |
| RoHS Status | [DATA_NEEDED: rohs_status] | β |
| Typical Gates | β | 200,000 |
| Maximum Logic Elements | β | 8320 |
| Macros / Logic Cells | β | 832 |
| Maximum Flip-Flops | β | 13,824 |
| Embedded RAM | β | 53,248 bits |
| User I/Os | β | 271 |
| Number of Terminals / Pins | β | 356 (LBGA) |
| Supply Voltage | β | 2.5 V (core) |
| Logic Family | β | CMOS |
| Number of PLLs | β | 4 embedded PLLs |
| Number of DDR Interfaces | β | 4 |
| Package Type | β | 356-LBGA (EBC suffix) |
| Speed Grade | β | -2 |
| Compliance | β | RoHS status [DATA_NEEDED: RoHS] |