EP20K200EBC356-2 - APEX 20KE 200K Gates FPGA 356-LBGA | Altera
MPN: EP20K200EBC356-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $179.73 | $179.73 |
| 10 | $162.5 | $1,625.00 |
| 100 | $145 | $14,500.00 |
| 500 | $122 | $61,000.00 |
| 1,000 | $99.5 | $99,500.00 |
EP20K200EBC356-2 Overview
A Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that combines a large number of configurable logic blocks (CLBs), programmable interconnect, and embedded memory and multiplier blocks. FPGAs sit within the hierarchy of programmable logic devices -> CPLDs -> programmable logic devices -> semiconductors, providing ASIC-like integration with field-reprogrammability. The APEX 20KE family pioneered MultiCore architecture integrating look-up tables (LUTs) and embedded dual-port RAM.
Key features of the EP20K200EBC356-2 include 200K typical gates, 832 macrocells, 13,824 maximum flip-flops, 53,248 bits of embedded RAM, four embedded Phase-Locked Loops (PLLs) for clock management, and four DoubleDataRate (DDR) interfaces. It supports multiple I/O standards including LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, HSTL, LVDS, and LVPECL, enabling flexible interfacing to memory, processors, and high-speed backplanes.
The -2 speed grade denotes a balance between performance and power, with the commercial operating temperature range of 0 to 85 C. The LBGA-356 package provides high signal density for I/O-rich applications. Quartus and MAX+PLUS II design tools support the APEX 20KE family, with legacy IP cores available through Altera's documentation archive.
Typical applications include telecommunications switching, ATM backbone packet processing, high-speed data-path bridging, video processing pipelines, and DSP co-processing in industrial control and military systems. The wide I/O count (271) and embedded RAM make it well-suited for buffering large data streams.
When designing with this part, ensure proper decoupling with 0.1 uF and 10 uF capacitors placed close to every power pin. The LBGA-356 package requires X-ray inspection or BGA rework capability for prototype bring-up. Verify pin assignments using the Altera pin-out file because the BGA ball map differs from earlier APEX 20K packages.
This page synthesizes distributor stock, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for EP20K200EBC356-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K200EBC356-2 (same form factor and footprint) — differing in Family, Operating Temperature, Package, Series, Mounting Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K200EBC356-1
✅ Drop-In✓ In Stock
$142 / Unit
View Datasheet →EP20K200EBC356-2X
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K200EBC356-2N
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K200CB356C8N
✅ Drop-In✓ In Stock
$56.4 / Unit
View Datasheet →EP20K100EBC356-3N
✅ Drop-In✓ In Stock
$92 / Unit
View Datasheet →EP20K200EBC356-2 Maximum Ratings & Electrical Characteristics
| Series | APEX 20KE |
| Family | APEX 20K (APEX 20KE enhancement) |
| Typical Gates | 200,000 |
| Maximum Logic Elements | 8320 |
| Macros / Logic Cells | 832 |
| Maximum Flip-Flops | 13,824 |
| Embedded RAM | 53,248 bits |
| User I/Os | 271 |
| Number of Terminals / Pins | 356 (LBGA) |
| Propagation Delay | 2.5 ns |
| Supply Voltage | 2.5 V (core) |
| Operating Temperature | 0 C to 85 C (commercial) |
| Logic Family | CMOS |
| Number of PLLs | 4 embedded PLLs |
| Number of DDR Interfaces | 4 |
| Package Type | 356-LBGA (EBC suffix) |
| Mounting Type | Surface Mount (BGA) |
| Speed Grade | -2 |
EP20K200EBC356-2 Pin Configuration
| Pin A1 | I/O / GND — User I/O or ground per BGA ball map |
| Pin A2 | I/O / GND — User I/O or ground per BGA ball map |
| Pin A3 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin A4 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin A5 | VCCIO — I/O supply reference |
| Pin B1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin B2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin B3 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin B4 | GND — Ground |
| Pin B5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin C1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin C2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin C3 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin C4 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin C5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin D1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin D2 | VCCINT — Core supply 2.5V |
| Pin D3 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin D4 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin D5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin E1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin E2 | GND — Ground |
| Pin E3 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin E4 | VCCIO — I/O supply reference |
| Pin E5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin F1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin F2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin F3 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin F4 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin F5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin G1 | GND — Ground |
| Pin G2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin G3 | PLL1_OUT — PLL clock output (PLL bank 1) |
| Pin G4 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin G5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin H1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin H2 | VCCA_PLL — PLL analog supply |
| Pin H3 | PLL1_IN — PLL clock input (PLL bank 1) |
| Pin H4 | GND — Ground |
| Pin H5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin J1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin J2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin J3 | nCONFIG — Configuration control (active-low) |
| Pin J4 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin J5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin K1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin K2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin K3 | MSEL0 — Configuration mode select |
| Pin K4 | MSEL1 — Configuration mode select |
| Pin K5 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin L1 | GND — Ground |
| Pin L2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin L3 | nSTATUS — Configuration status (active-low) |
| Pin L4 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin L5 | VCCIO — I/O supply reference |
| Pin M1 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin M2 | I/O — User I/O bank per APEX 20KE pinout file |
| Pin M3 | DATA0 — Configuration data bit 0 |
| Pin M4 | DCLK — Configuration clock |
| Pin M5 | I/O — User I/O bank per APEX 20KE pinout file |
Typical Applications
EP20K200EBC356-2 is suitable for 6 applications: Telecommunications Switching and ATM Backbones, High-Speed Data Path Bridging, Video Processing Pipelines, DSP Co-Processing in Industrial Control, Military and Aerospace Avionics Interfaces, System-on-a-Programmable-Chip (SOPC) Integration.
Telecommunications Switching and ATM Backbones
The EP20K200EBC356-2 fits telecom switching fabrics through its 200K system gates, 53,248 bits of embedded RAM, and 271 user I/Os. The 53 Kbits of dual-port RAM enables cell-buffer storage for ATM AAL-2/5 segmentation and reassembly without external SRAM, while 271 I/Os drive UTOPIA-level interfaces to PHY and SERDES devices. The four embedded PLLs synthesize multiple clock domains (TDM bus, fabric, PHY reference) from a single backplane clock. According to APEX 20KE datasheet, the LVDS and LVPECL I/O standards directly support telecom backplane serial links, eliminating external transceivers for short-reach connections and reducing BOM cost in high-density switching systems.
Recommended
High-Speed Data Path Bridging
The EP20K200EBC356-2 fits data-path bridging between legacy buses (PCI, GTL+, HSTL) and modern DDR or RapidIO interfaces. Its four DDR interfaces support DDR-SDRAM at up to 133 MHz, while 13,824 flip-flops enable wide-width pipeline registers for stream processing. The 832 macros provide logic capacity to implement protocol bridges (PCI-to-LocalBus, H.110 to Utopia) within a single device, simplifying board layout. According to APEX 20KE application notes, the LVDS I/O standard directly drives differential backplanes at gigabit rates, and the 53 Kbits of embedded RAM serve as elastic FIFOs across clock domains. This part is well-matched when the bridge needs both LVTTL legacy support and modern LVDS signaling in one chip.
Recommended
Video Processing Pipelines
The EP20K200EBC356-2 fits video processing because its 200K gates implement line buffers, color-space converters, and motion-compensation logic for SDTV to HDTV format conversion. The 53 Kbits of embedded RAM serve as multi-line video buffers (typical line width is 720-1920 pixels), while 271 I/Os accommodate ITU-R BT.656, BT.1120, and proprietary parallel video interfaces. The four embedded PLLs generate pixel clocks from a single video reference, and SSTL-2/3 I/O standards directly interface DDR2 memory for frame buffering. According to APEX 20KE datasheet, the device's 2.5 ns propagation delay sustains real-time processing of SDI streams at 270 Mbps and 1.485 Gbps rates common in broadcast video applications.
Recommended
DSP Co-Processing in Industrial Control
The EP20K200EBC356-2 fits DSP co-processing by implementing parallel FIR filters, FFT engines, and motor-control algorithms alongside a host processor. The 832 macros map to dedicated multiplier cascades or soft DSP cores (Nios equivalents), and the 53 Kbits of embedded RAM hold coefficient tables and intermediate buffers. The 271 I/Os interface to industrial sensors (LVTTL/HSTL), encoders (LVDS for high-noise environments), and motor-driver PWM signals. According to APEX 20KE documentation, the 2.5V core operates reliably in industrial temperature ranges when ordered in the appropriate suffix, and the 356-LBGA package withstands vibration in machinery mounting. This part is well-suited for closed-loop control requiring deterministic hardware acceleration of DSP kernels.
Recommended
Military and Aerospace Avionics Interfaces
The EP20K200EBC356-2 in extended temperature variants fits avionics interfaces through its wide I/O count and MIL-STD-1553 / ARINC 429 protocol support in soft IP. The 271 user I/Os drive multiple avionics buses simultaneously, while 200K gates implement protocol engines, error checking, and signal-conditioning logic. The four PLLs generate multiple bus-rate clocks from a single reference, and LVDS I/Os provide noise immunity in EMI-rich cockpit environments. According to APEX 20KE datasheet, the silicon supports extended temperature when ordered in 'I' or 'M' suffix variants. This part is well-matched when avionics designers need a high-density, field-upgradable logic device with long-term support from authorized distributors like Rochester Electronics for legacy sustainment programs.
Recommended
System-on-a-Programmable-Chip (SOPC) Integration
The EP20K200EBC356-2 fits SOPC integration by embedding processor cores, peripherals, custom logic, and memory interfaces in a single chip. The 832 macros accommodate 32-bit Nios-equivalent soft processors plus peripherals (UART, SPI, timers), while 53 Kbits of embedded RAM hold program code and data buffers. The 271 I/Os expose system buses (PCI, Avalon-like interfaces) to external memory and ASIC companions. According to Altera's APEX 20KE documentation, the MultiCore architecture pioneered combining LUTs and embedded dual-port RAM, making it ideal for early SOPC designs. This part is well-suited when designers need a single-device platform that consolidates CPU, glue logic, and high-speed I/O, reducing PCB complexity and BOM cost.
Recommended
Recommended Products Summary
Engineering reference data for EP20K200EBC356-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K200EBC356-1 | EP20K200EBC356-2X | EP20K200EBC356-2N | EP20K200CB356C8N | EP20K100EBC356-3N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 356-LBGA (EBC) | 356-LBGA (EBC) - same | 356-LBGA (EBC) - same | 356-LBGA (EBC) - same | 356-LBGA (CB prefix) - same BGA footprint | 356-LBGA (EBC) - same |
| Family | APEX 20KE | APEX 20KE | APEX 20KE | APEX 20KE | APEX 20K (base, no E) | APEX 20KE |
| Typical Gates | 200,000 | 200,000 | 200,000 | 200,000 | 200,000 | 100,000 |
| Macros | 832 | 832 | 832 | 832 | 832 | 416 |
| User I/Os | 271 | 271 | 271 | 271 | 271 | 246 |
| Embedded PLLs | 4 | 4 | 4 | 4 | 0 (no E suffix) | 4 |
| Speed Grade | -2 | -1 (slower) | -2X (extended) | -2N (industrial handling) | -8 speed grade | -3N |
| Supply Voltage | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Lifecycle Status | Obsolete (2026) | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Faster speed grade for higher Fmax (vs EP20K200EBC356-1)
- Extended temperature / lead-free variant (vs EP20K200EBC356-2X)
- Embedded PLLs vs base family (vs EP20K200CB356C8N)
Design Notes
Estimated: at 2.5V VCCINT, the APEX 20KE core current draw scales with toggle rate; at full 200K-gate utilization and 100 MHz toggle rate, expect approximately 500-800 mA core current (estimated, datasheet ICCINT is gated by configuration mode). Place one 0.1 uF X7R ceramic bypass cap on every VCCINT pin and bulk-decouple with 4-6 x 10 uF tantalum or ceramic per power rail. PLL analog supply (VCCA_PLL) requires a low-noise filtered 2.5V derived through a ferrite bead to minimize jitter. According to APEX 20KE datasheet power-section guidance, separate VCCIO banks if mixing LVTTL and LVDS I/O standards on the same device to avoid supply-coupling noise.
The 356-LBGA (EBC) package requires a 1.0 mm or 1.27 mm pitch BGA land pattern with via-in-pad or dog-bone fan-out per PCB fab capability. Floor planning should reserve at least 4 layers for power/ground planes, with the top layer dedicated to fine fan-out routing and inner layers for power planes and signal breakout. Place all configuration pins (nCONFIG, nSTATUS, DCLK, DATA[0..7], MSEL[0..2]) in a routing-friendly region near the configuration EEPROM. According to APEX 20KE layout guidelines, all I/O banks should have continuous VCCIO power planes underneath to maintain signal integrity for LVDS and SSTL signaling.
Do not substitute the EBC-356 BGA package pinout with the older EP20K200BC356-2 (APEX 20K base) without cross-checking the pin-out file - the ball map differs between generations even when the package code looks similar. Verify configuration mode via MSEL[0..2] settings against the chosen configuration EEPROM (EPC16, EPC8, EPC4). Mixed-voltage I/O banks must use a common reference voltage for any differential pair; SSTL-2 and SSTL-3 standards are NOT interchangeable. Note: this part is obsolete (as of 2026-09-07), so design for test should plan for last-time-buy and lifecycle sustainment through authorized distributors such as Rochester Electronics.
Estimated: at typical operating toggle rates, the 356-LBGA APEX 20KE device dissipates approximately 1.5-2.5 W, well within the 1-layer JEDEC test-board thermal envelope. For high-utilization designs with sustained toggle rates above 50 MHz on 80%+ of logic elements, expect junction temperatures approaching 100 C in commercial-temperature applications. Use 4 thermal vias per BGA pad array under the die region to conduct heat to inner ground planes. According to APEX 20KE datasheet thermal section, the device's thermal resistance theta-JA is package-dependent; consult the package-specific thermal characterization report for production thermal budgets.
Compliance Information
RoHS, REACH, and lead-free status not specified in verified web data; Altera APEX 20KE family generally pre-dates RoHS mandates (the family launched ~1999-2002), so the -2 base part may be non-compliant; EP20K200EBC356-2X is the lead-free variant. Consult the manufacturer declaration of conformity (MDC) for current compliance status.
