EP20K1500EBC652-1X vs EP20K1000EBC652-2X Comparison

Detailed side-by-side comparison of EP20K1500EBC652-1X by Altera and EP20K1000EBC652-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K1500EBC652-1X EP20K1000EBC652-2X
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $175.00 $99.00
Family APEX 20KE APEX-20KE
Logic Elements / Cells 51840 β€”
System Gates 1.5 M β€”
Macros 3456 β€”
Total RAM Bits 442368 β€”
User I/O 488 β€”
Number of I/O Banks [DATA_NEEDED: I/O bank count] β€”
Propagation Delay 1.84 ns 1.6 ns
Internal Frequency 160 MHz (per digchip) / 400 MHz (per fpgakey) β€”
Core Voltage 1.8 V 1.8 V
Process Technology 0.22 Β΅m CMOS 0.22 Β΅m (some sources 0.15 Β΅m) all-layer copper-metal CMOS
Operating Temperature 0 Β°C to +85 Β°C (commercial) 0 Β°C to +85 Β°C (commercial)
Package 652-ball BGA (FCBGA / PBGA652) 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch)
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL rating] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] Compliant
Configuration Method JTAG / SRAM β€”
Architecture MultiCore (LUT + product-term) β€”
Device Logic Elements β€” 38,400
Typical Gates β€” 1,000,000 system gates
Embedded Memory Bits β€” 327,680 bits
User I/O Pins β€” 488
Maximum User I/O β€” 488
Internal Maximum Frequency β€” 350 MHz
Logic Blocks / Macros β€” 2,560 macros
PLLs β€” 4
Configuration Interface β€” JTAG (IEEE 1149.1), Passive Serial, Altera configuration

Datasheets & Resources

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