EP20K200CF484I7 vs EP20K200CF484C9N Comparison
Detailed side-by-side comparison of EP20K200CF484I7 by Altera and EP20K200CF484C9N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K200CF484I7 - APEX 20KC 200K Gates FPGA 1.8V FBGA-484 | Altera
EP20K200CF484I7 β Last Time Buy
Specification Comparison
| Parameter | EP20K200CF484I7 | EP20K200CF484C9N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $89.50 | $201.04 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 8,320 | 8,320 |
| Typical Gate Count | 200,000 system gates | β |
| Maximum Operating Frequency | 375.94 MHz (per device-family data) | β |
| Process Technology | 0.15 Β΅m CMOS with copper interconnect | 0.15 um CMOS |
| Internal Supply Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | β |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| User I/O Pins | 376 | β |
| Dedicated Inputs | 4 | β |
| Package | 484-pin FBGA (FineLine BGA) | 484-pin FineLine BGA (FBGA) |
| Package Body Size | 23 mm Γ 23 mm | β |
| Ball Pitch | 1.000 mm | β |
| Speed Grade | -7 | C9 (250 MHz) |
| Temperature Grade (I7 suffix) | Industrial, -40 Β°C to +85 Β°C | β |
| Configuration Technology | SRAM-based, re-programmable in-system | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Propagation Delay | [DATA_NEEDED: datasheet-specified tpd] | β |
| Device Type | β | FPGA (Field-Programmable Gate Array) |
| Typical Gates | β | 200,000 |
| Embedded System Block (ESB) Bits | β | 106,496 |
| Maximum User I/O | β | 376 |
| Maximum Clock Frequency | β | 250 MHz |
| Core Supply Voltage (VCCINT) | β | 1.8 V |
| Temperature Grade | β | Industrial (0C to +85C) |
| Mounting Type | β | Surface Mount (BGA) |
| Configuration Scheme | β | SRAM-based, supports passive serial/parallel and JTAG |
| MSL Level | β | 3 (per JEDEC J-STD-020) |