EP20K200CF672C8ES vs EP20K400CF672C8ES Comparison
Detailed side-by-side comparison of EP20K200CF672C8ES by Intel and EP20K400CF672C8ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K200CF672C8ES | EP20K400CF672C8ES |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $158.00 | $158.40 |
| Family | APEX 20K | APEX 20KC |
| Maximum Logic Elements | 8,320 | β |
| Typical Gates | 200,000 system gates | β |
| Maximum User I/O Pins | 1,064 | β |
| Embedded RAM Bits | 212,992 bits | β |
| Package | 672-ball FineLine BGA | 672-BGA FineLine (FC-FBGA / S-PBGA-B672) |
| Speed Grade | C8 (8 ns pin-to-pin) | β |
| Operating Temperature | 0C to +85C (commercial) | 0Β°C to 85Β°C (Commercial) |
| Core Voltage | 1.8 V | β |
| Configuration Method | SRAM, requires external PROM | β |
| Process Technology | [DATA_NEEDED: process node] | 0.15 Β΅m CMOS |
| Mounting Type | Surface Mount (BGA) | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: not stated in verified data] |
| Status Suffix | ES (Engineering Sample) | β |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL | β |
| Logic Element Architecture | 4-input LUT with dedicated carry/cascade | β |
| Embedded Memory Type | RAM / ROM / CAM blocks | β |
| Series | β | EP20K400 |
| Logic Cells / Macros | β | 16,640 |
| System Gates (typical) | β | 400,000 |
| System Gates (maximum) | β | 212,992 [DATA_NEEDED: confirm datasheet interpretation] |
| Maximum User I/O | β | 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value] |
| Bidirectional I/O | β | 484 |
| Propagation Delay | β | 2.5 ns |
| Maximum Internal Frequency | β | 301.21 MHz |
| Nominal Supply Voltage | β | 1.8 V |
| Supply Voltage Range | β | 1.71 V to 1.89 V |
| Logic Family | β | CMOS |
| Architecture | β | MultiCoreβ’ (LUT + Embedded System Block) |
| Programming Method | β | JTAG / in-system via configuration memory |