EP20K200CF672C8ES - APEX 20K 200K Gate FPGA 672-BGA | Intel
MPN: EP20K200CF672C8ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $245 | $245.00 |
| 10 | $220.5 | $2,205.00 |
| 100 | $195 | $19,500.00 |
| 500 | $175 | $87,500.00 |
| 1,000 | $158 | $158,000.00 |
EP20K200CF672C8ES Overview
An FPGA (Field-Programmable Gate Array) is a type of programmable logic device (PLD) that engineers can configure after manufacturing to implement arbitrary digital circuits. Within the broader semiconductor hierarchy, FPGAs sit alongside microcontrollers and ASICs as flexible digital platforms. APEX 20K belongs to Intel's (Altera's) earlier-generation PLD portfolio, positioned between CPLDs (smaller, non-volatile, lower-density) and modern high-end FPGAs (millions of logic elements, multi-Gbps transceivers). The MultiCore architecture combines logic elements (LEs), embedded system blocks (ESBs) for memory and specialized functions, and a high-bandwidth interconnect fabric.
Key features of the EP20K200CF672C8ES include a maximum of 212,992 bits of embedded RAM distributed across embedded system blocks, 1,064 maximum user I/O pins, and an LVTTL/LVCMOS-compatible I/O standard set. The device supports in-system programmability via SRAM configuration, requires a separate configuration device (e.g., EPC2) for standalone boot, and operates on a 1.8V core supply with I/O banks supporting multiple voltage standards. The "C8" speed grade corresponds to commercial temperature range (-0°C to +85°C) and an 8 ns pin-to-pin delay, while the "ES" suffix indicates an engineering sample.
The APEX 20K architecture uses a four-input look-up table (LUT4) per LE, with dedicated carry chains for arithmetic and dedicated cascade chains for wide fan-in functions. Embedded system blocks can be configured as RAM, ROM, or CAM (Content-Addressable Memory), allowing the device to implement true dual-port memories, FIFOs, and lookup-table-based DSP operations without external memory. The high I/O count (1,064 maximum) is achieved through the FineLine BGA package, which uses an array-style footprint.
Typical applications include 10/100/Gigabit Ethernet bridging, ATM/SONET/SDH framer implementations, custom DSP datapaths, and high-speed bus interface logic for PCI, PCI-X, and proprietary backplanes. The high embedded-memory density makes the EP20K200CF672C8ES particularly attractive for designs that require on-chip packet buffering, look-up tables for routing, or large register files. The 672-pin FineLine BGA package provides signal integrity advantages for high-frequency interfaces.
When designing with this device, plan for configuration memory (typically an EPC2 or EPC16 companion PROM), a JTAG boundary-scan chain for board-level testability, and careful power-rail decoupling because the 1.8V core can draw substantial current during simultaneous-switching events on output pins. The engineering sample (ES) status means this specific part number is intended for prototyping and qualification; production builds should target the equivalent commercial suffix without "ES".
This page synthesizes distributor pricing, drop-in same-package alternatives from the Site MPN list, and practical design notes that complement the manufacturer datasheet. Pricing references are stated as of 2026-09-07.
Drop-in alternatives for EP20K200CF672C8ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K200CF672C8ES (same form factor and footprint) — differing in Family, Package, Operating Temperature, Process Technology, Speed Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K200CF672C7ES
✅ Drop-In✓ In Stock
$220 / Unit
View Datasheet →EP20K200CF672C8N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP20K200CF672C9N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP20K200CF672C9ES
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K200CF672C8
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K200CF672I8N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP20K200CF672C8ES Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Maximum Logic Elements | 8,320 |
| Typical Gates | 200,000 system gates |
| Maximum User I/O Pins | 1,064 |
| Embedded RAM Bits | 212,992 bits |
| Package | 672-ball FineLine BGA |
| Speed Grade | C8 (8 ns pin-to-pin) |
| Operating Temperature | 0C to +85C (commercial) |
| Core Voltage | 1.8 V |
| Configuration Method | SRAM, requires external PROM |
| Mounting Type | Surface Mount (BGA) |
| Status Suffix | ES (Engineering Sample) |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL |
| Logic Element Architecture | 4-input LUT with dedicated carry/cascade |
| Embedded Memory Type | RAM / ROM / CAM blocks |
EP20K200CF672C8ES Pin Configuration
| Pin B1 | I/O BANK 1 — User I/O, LVTTL/LVCMOS |
| Pin B26 | I/O BANK 2 — User I/O |
| Pin AA1 | I/O BANK 7 — User I/O |
| Pin AA26 | I/O BANK 8 — User I/O |
| Pin D5 | VCCINT — 1.8V core supply |
| Pin D22 | VCCINT — 1.8V core supply |
| Pin AC3 | VCCIO1 — I/O bank 1 reference voltage |
| Pin AC24 | VCCIO8 — I/O bank 8 reference voltage |
| Pin F2 | GND — Common ground |
| Pin F25 | GND — Common ground |
| Pin H1 | DCLK — Configuration clock input |
| Pin H26 | nCONFIG — Configuration start (active low) |
| Pin K4 | CONF_DONE — Configuration complete (open-drain) |
| Pin K23 | nSTATUS — Configuration status (active low) |
| Pin N7 | MSEL0 — Configuration mode select 0 |
| Pin N20 | MSEL1 — Configuration mode select 1 |
| Pin Q10 | TCK — JTAG clock |
| Pin Q17 | TMS — JTAG mode select |
| Pin T13 | TDI — JTAG data input |
| Pin T14 | TDO — JTAG data output |
Typical Applications
EP20K200CF672C8ES is suitable for 6 applications: 10/100/Gigabit Ethernet Bridge, ATM / SONET / SDH Framer, Custom DSP Datapath, PCI / PCI-X Bus Interface, Industrial Control Logic, High-Speed Custom Bus Bridge.
10/100/Gigabit Ethernet Bridge
The EP20K200CF672C8ES is well-suited to Ethernet bridging applications because its 212,992 bits of embedded RAM provide on-chip packet buffering for store-and-forward or cut-through switching architectures, while the 1,064 available user I/O pins accommodate multiple GMII/RGMII/SGMII interfaces plus dedicated PHY MDIO buses. The MultiCore embedded system blocks can be configured as true dual-port RAM for descriptor FIFOs and statistics counters, replacing external SSRAM. With an 8 ns C8 pin-to-pin delay and LVTTL/LVCMOS I/O standards, the device can implement a 4-port Gigabit Ethernet bridge at wire speed without external glue logic. The 672-ball FineLine BGA footprint supports the high signal count required for multi-port MAC and PHY interconnect.
Recommended
ATM / SONET / SDH Framer
Telecommunications framer designs benefit from the EP20K200CF672C8ES's combination of 8,320 logic elements for HDLC framing, cell delineation, and pointer-processing state machines, alongside embedded RAM for payload pointer queues and jitter buffers. The 200K system gates are sufficient to implement an OC-48 (2.5 Gbps) framer with header-error-control, scrambling/descrambling, and path-overhead insertion, while the 672-ball FineLine BGA package provides low-skew differential-pair routing for HSTL/SSTL interfaces to SERDES devices. The C8 8 ns timing meets the throughput requirements of ATM cell delineation at 155 Mbps (STM-1). The FPGA's CAM blocks are ideal for VPI/VCI lookup tables required in ATM switching fabrics.
Recommended
Custom DSP Datapath
The EP20K200CF672C8ES is well-matched to custom DSP applications because its 4-input LUT logic elements implement fast multiply-accumulate structures, and the 212,992 bits of embedded RAM serve as coefficient tables and delay-line buffers for FIR/IIR filters without external memory. At 8 ns C8 speed grade, the device can sustain 125 MHz operation in pipelined FIR filter configurations, achieving DSP throughput comparable to mid-range dedicated DSP processors while preserving reconfigurability. The 672-ball BGA package supports the parallel data buses typical of high-sample-rate ADC/DAC interfacing. Engineers can implement FFT butterflies, correlators, and adaptive filters entirely in the APEX 20K fabric.
Recommended
PCI / PCI-X Bus Interface
The EP20K200CF672C8ES supports 32-bit/33 MHz PCI and 64-bit/66 MHz PCI-X interfaces directly through its LVTTL/PCI-compliant I/O banks, allowing it to function as a bus master or target device without external bridge chips. The 1,064 user I/O pins accommodate the 64-bit PCI-X bus plus additional side-band signals (REQ, GNT, IDSEL, INTA-INTD, PERR, SERR, PAR) plus local-bus expansion. With 8,320 logic elements, the device can implement scatter-gather DMA engines, message-signaled interrupt controllers, and configuration-space registers in a single chip. The 672-ball FineLine BGA footprint preserves signal integrity for the 66 MHz PCI-X clock edge rates.
Recommended
Industrial Control Logic
Industrial control applications benefit from the EP20K200CF672C8ES's abundant logic resources for implementing encoder/decoders, quadrature counters, motion-control state machines, and protocol bridges (Modbus, Profibus, CANopen) without offloading to external microcontrollers. The 212 Kbit embedded RAM serves as table storage for PID coefficients, lookup-based waveform synthesis, and circular-logger buffers. The 672-ball BGA's 1,064 I/O count supports dozens of optically-isolated digital inputs, PWM outputs, and encoder interfaces simultaneously. The 8 ns C8 speed grade enables deterministic cycle times in real-time control loops. For harsher environments, drop-in replacement with the EP20K200CF672I8N industrial-temperature variant is available.
Recommended
High-Speed Custom Bus Bridge
The EP20K200CF672C8ES is well-matched to high-speed proprietary backplane-bridge designs because its 1,064 user I/O pins can simultaneously drive multiple parallel buses (e.g., 32-bit local bus plus 64-bit interconnect bus), while the 8,320 logic elements implement custom protocol translation, FIFO, and flow-control logic in a single device. Embedded system blocks configured as true dual-port RAM implement cross-clock-domain FIFOs, eliminating the need for external SSRAM. The 212 Kbit embedded RAM also supports error-correction code (ECC) generation/checking tables and address-lookup tables for memory-mapped bridges. The 672-ball FineLine BGA package maintains controlled-impedance routing for sub-nanosecond edge rates.
Recommended
Recommended Products Summary
Engineering reference data for EP20K200CF672C8ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K200CF672C7ES | EP20K200CF672C8N | EP20K200CF672C9N | EP20K200CF672C9ES | EP20K200CF672C8 | EP20K200CF672I8N |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FineLine BGA | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| System Gates | 200,000 | 200,000 | 200,000 | 200,000 | 200,000 | 200,000 | 200,000 |
| Logic Elements | 8,320 | 8,320 | 8,320 | 8,320 | 8,320 | 8,320 | 8,320 |
| Embedded RAM Bits | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 |
| Speed Grade | C8 (8 ns) | C7 (7 ns) | C8 (8 ns) | C9 (9 ns) | C9 (9 ns) | C8 (8 ns) | I8 (8 ns) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Status Suffix | ES (Engineering Sample) | ES (Engineering Sample) | N (Lead-free) | N (Lead-free) | ES (Engineering Sample) | Standard | N (Lead-free) |
| Unit Price (qty 1, USD) | 245.00 | 235.00 | 255.00 | 230.00 | 240.00 | 215.00 | 275.00 |
Key Differentiators
- Highest I/O count available in APEX 20K family (672-ball BGA) (vs EP20K200CF484I9)
- Higher logic capacity vs APEX 20K100 (vs EP20K100CF324C8ES)
- Embedded system blocks configurable as CAM for fast table matching (vs CPLD-class devices (e.g. MAX 7000))
Design Notes
The EP20K200CF672C8ES requires a low-noise 1.8V core supply (VCCINT) capable of delivering 1.0 to 2.0 A during configuration and peak dynamic operation. Decoupling strategy: place 0.1 uF X7R ceramic capacitors within 5 mm of every VCCINT ball, with bulk 47 uF tantalum or polymer capacitors at the regulator output. I/O banks (VCCIO1 through VCCIO8) require their own reference voltages matching the chosen I/O standard (3.3V for LVTTL/LVCMOS, 2.5V for LVCMOS2.5, 1.5V for HSTL). Simultaneous-switching output events on 32+ outputs can cause ground-bounce; suppress with series damping resistors or driver-strength settings in Quartus.
The 672-ball FineLine BGA package requires a multilayer PCB with controlled-impedance routing and a fanout pattern using 0.5 mm-pitch microvias or dog-bone fanout to inner signal layers. BGA escape routing should reserve two outer PCB layers for full ball breakout; signal pairs should maintain 100 ohm differential impedance. Decoupling capacitors must be placed on the opposite side of the BGA within 2-3 mm of the package balls. Thermal vias under the package center pad improve heat dissipation to inner ground planes. For JTAG chain access, route TMS/TCK/TDI/TDO to a 0.1-inch header for boundary-scan testability.
Common pitfalls when designing with the EP20K200CF672C8ES: (1) do not omit the external configuration PROM (EPC2, EPC8, or EPC16) - the device is SRAM-based and loses configuration on power-down; (2) ensure MSEL0/MSEL1 pin settings match the intended configuration mode (AS, PS, JTAG, or controller); (3) verify all VCCINT and VCCIO supply rails are monotonic during power-up to prevent partial configuration; (4) respect the 1.8V VCCINT absolute maximum - applying 3.3V will permanently damage the core; (5) ensure the CONF_DONE pin is pulled high via external resistor to indicate successful configuration; (6) the "ES" engineering sample suffix means pre-production silicon - production builds should use the standard or N-suffix equivalent.
The EP20K200CF672C8ES features 1,064 user I/O pins distributed across eight I/O banks; clock signals (DCLK, JTAG TCK, high-speed LVDS) should be routed on inner stripline layers with reference planes to control impedance. Apply series termination (22-33 ohm) on clock outputs to dampen reflections. For PCI/PCI-X applications, maintain 50-65 ohm impedance and place the device within 25 mm of the bus connector to meet PCI signal-integrity specifications. The APEX 20K MultiCore architecture uses a high-bandwidth interconnect fabric that propagates long combinatorial paths; register long combinational chains and pipeline aggressively to meet timing closure in Quartus.
Compliance Information
Compliance data not present in verified web sources. APEX 20K family is an older Intel/Altera FPGA line predating widespread RoHS/REACH disclosure requirements; consult Intel Product Change Notifications or PCN documents for specific compliance statements. N-suffix variants (e.g., EP20K200CF672C8N) are typically lead-free per Altera convention.
