EP20K200EBC356-2 vs EP20K100EBC356-3N Comparison

Detailed side-by-side comparison of EP20K200EBC356-2 by Altera and EP20K100EBC356-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K200EBC356-2 EP20K100EBC356-3N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $99.50 $92.00
Series APEX 20KE APEX-20KE
Family APEX 20K (APEX 20KE enhancement) APEX 20K
Typical Gates 200,000 β€”
Maximum Logic Elements 8320 β€”
Macros / Logic Cells 832 β€”
Maximum Flip-Flops 13,824 β€”
Embedded RAM 53,248 bits β€”
User I/Os 271 β€”
Number of Terminals / Pins 356 (LBGA) β€”
Propagation Delay 2.5 ns 1.6 ns (speed grade -3N)
Supply Voltage 2.5 V (core) β€”
Operating Temperature 0 C to 85 C (commercial) 0 Β°C to +85 Β°C
Logic Family CMOS β€”
Number of PLLs 4 embedded PLLs β€”
Number of DDR Interfaces 4 β€”
Package Type 356-LBGA (EBC suffix) β€”
Mounting Type Surface Mount (BGA) Surface Mount
Speed Grade -2 β€”
Compliance RoHS status [DATA_NEEDED: RoHS] β€”
Logic Elements / Cells β€” 4160
System Gates β€” 100,000
Embedded Memory (bits) β€” 53,248
Embedded System Blocks (ESBs) β€” 26
Maximum User I/Os β€” 246
Number of Pins β€” 356
Package β€” 356-LBGA (Ball Grid Array)
Package Dimensions β€” 45 x 45 mm
Ball Pitch β€” 1.27 mm
Process Technology β€” 0.22 Β΅m CMOS
Core Supply Voltage β€” 1.8 V
Maximum Internal Frequency β€” 250 MHz
Programmable Interface β€” JTAG (IEEE 1149.1)
I/O Standards Supported β€” LVCMOS, LVTTL, PCI, SSTL-2/3, GTL+
RoHS Status β€” [DATA_NEEDED: rohs_status]

Datasheets & Resources

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