EP20K200EQC208-3 vs EP20K200CF484C8ES Comparison
Detailed side-by-side comparison of EP20K200EQC208-3 by Intel and EP20K200CF484C8ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K200EQC208-3 | EP20K200CF484C8ES |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $65.00 | $89.00 |
| Family | APEX 20KE | APEX 20K |
| Series | APEX 20K (enhanced "E" variant) | APEX-20KC |
| Product Type | FPGA (Field Programmable Gate Array), SRAM-based, in-system programmable | β |
| System Gates (typical) | 200,000 | β |
| Logic Elements (LEs) | 8,320 | β |
| Embedded RAM Bits | 106,496 | β |
| Maximum User I/O | 136 | β |
| Speed Grade | -3 | C8 (-8 commercial) |
| Core Supply Voltage (VCCINT) | 2.5 V (typical, APEX 20KE generation) | β |
| I/O Supply Voltage (VCCIO) | MultiVolt, 1.8 V / 2.5 V / 3.3 V / 5 V compatible | β |
| Package | 208-BFQFP / PQFP208 (Plastic Quad Flat Pack, gull-wing) | 484-pin FBGA (FineLine BGA) |
| Terminal Pitch | 0.5 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Technology | CMOS, SRAM configuration cell | β |
| Configuration Mode | Fast Passive Parallel (FPP), Passive Serial (PS), JTAG (IEEE 1149.1) | β |
| Embedded Array Blocks (EABs) | Yes (dual-port RAM/ROM, up to 16-bit wide) | β |
| MultiVolt I/O Support | Yes | β |
| LVDS Support | True-LVDS (enhanced "E" variant feature) | β |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Operating Temperature (Commercial) | 0 Β°C to 85 Β°C | β |
| Logic Elements | β | 8,320 |
| System Gates | β | 200,000 |
| Embedded Memory (RAM bits) | β | 106,496 |
| Number of Logic Array Blocks (LABs) | β | 104 |
| Number of Embedded System Blocks (ESBs) | β | 13 |
| User I/O Pins (max) | β | 376 |
| PLLs | β | 4 |
| Core Voltage | β | 1.8 V |
| Operating Temperature | β | 0C to +85C (commercial) |
| Process Node | β | 0.18 micron CMOS |
| Configuration Interface | β | JTAG (IEEE 1149.1) / Altera serial |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, GTL, SSTL, HSTL, AGP |
| Lead Free / RoHS | β | [DATA_NEEDED: lead-free status] |