EP20K200EQC208-3 vs EP20K200EBC652-3N Comparison
Detailed side-by-side comparison of EP20K200EQC208-3 by Intel and EP20K200EBC652-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K200EQC208-3 | EP20K200EBC652-3N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $65.00 | $220.00 |
| Family | APEX 20KE | โ |
| Series | APEX 20K (enhanced "E" variant) | APEX 20KE (APEX-20KEยฎ) |
| Product Type | FPGA (Field Programmable Gate Array), SRAM-based, in-system programmable | โ |
| System Gates (typical) | 200,000 | โ |
| Logic Elements (LEs) | 8,320 | โ |
| Embedded RAM Bits | 106,496 | โ |
| Maximum User I/O | 136 | โ |
| Speed Grade | -3 | -3 (slowest in APEX 20KE family) |
| Core Supply Voltage (VCCINT) | 2.5 V (typical, APEX 20KE generation) | โ |
| I/O Supply Voltage (VCCIO) | MultiVolt, 1.8 V / 2.5 V / 3.3 V / 5 V compatible | โ |
| Package | 208-BFQFP / PQFP208 (Plastic Quad Flat Pack, gull-wing) | 652-ball BGA |
| Terminal Pitch | 0.5 mm | โ |
| Mounting Type | Surface Mount | Surface Mount |
| Technology | CMOS, SRAM configuration cell | โ |
| Configuration Mode | Fast Passive Parallel (FPP), Passive Serial (PS), JTAG (IEEE 1149.1) | โ |
| Embedded Array Blocks (EABs) | Yes (dual-port RAM/ROM, up to 16-bit wide) | โ |
| MultiVolt I/O Support | Yes | โ |
| LVDS Support | True-LVDS (enhanced "E" variant feature) | โ |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | โ |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Operating Temperature (Commercial) | 0 ยฐC to 85 ยฐC | โ |
| Device Family | โ | EP20K200 |
| System Gates | โ | 200,000 |
| Logic Elements / Cells | โ | 8,320 |
| Logic Array Blocks (LABs) | โ | 832 |
| Macrocells | โ | 832 |
| Embedded RAM | โ | 106,496 bits |
| User I/Os (DigiKey listing) | โ | 376 |
| User I/Os (digchip listing) | โ | 277 |
| Propagation Delay | โ | 2.33 ns |
| Internal Frequency (max) | โ | 189 MHz |
| Process Technology | โ | 0.22 ยตm CMOS |
| Core Supply Voltage | โ | 1.71 V to 1.89 V (nominal 1.8 V) |
| I/O Supply (LVDS-capable) | โ | LVDS, 2.5 V referenced (per source variant) |
| Operating Temperature (TJ) | โ | 0 ยฐC to 85 ยฐC (commercial) |
| Configuration | โ | JTAG (IEEE 1149.1), Passive Serial |