EP20K200RC208-3 vs EP20K200RC208-2 Comparison

Detailed side-by-side comparison of EP20K200RC208-3 by Intel and EP20K200RC208-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K200RC208-3 EP20K200RC208-2
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $95.00 $79.67
Series APEX 20K APEX-20K
Family APEX-20Kยฎ APEX-20K MultiCore FPGA
Logic Elements / Cells 8,320 โ€”
Total System Gates 200,000 โ€”
Embedded Memory (bits) 106,496 106,496
Number of I/O Pins 144 โ€”
Package 208-RQFP Exposed Pad (BFQFP) 208-BQFP / 208-RQFP with Exposed Pad
Mounting Type Surface Mount Surface Mount
Process Technology 0.22 ยตm CMOS [DATA_NEEDED: process node]
Core Voltage 1.8 V โ€”
I/O Standard LVDS (3.3 V / 2.5 V) โ€”
Maximum Operating Frequency 167 MHz โ€”
PLLs 4 โ€”
Speed Grade -3 -2 (mid-speed, industrial)
Operating Temperature -40ยฐC to +85ยฐC (Industrial) -40C to +85C (industrial)
Programming Interface IEEE 1149.1 JTAG โ€”
In-System Programmable Yes โ€”
Hot Socketing Yes โ€”
RoHS Status Compliant [DATA_NEEDED: RoHS compliance]
Logic Elements (LEs) โ€” 8320
System Gates โ€” 200,000 (typical)
Maximum User I/O โ€” 144
Pin Count โ€” 208
Supply Voltage (Core) โ€” [DATA_NEEDED: core VCC]
Supply Voltage (I/O) โ€” 3.3 V (multi-standard I/O)
Configuration Interface โ€” JTAG (IEEE 1149.1) + Altera legacy scheme
MSL Level โ€” [DATA_NEEDED: MSL rating]
Lead-Free โ€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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