EP20K400BI652-2V vs EP20K400CB652C9ES Comparison
Detailed side-by-side comparison of EP20K400BI652-2V by Intel and EP20K400CB652C9ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400BI652-2V - 400K Gates APEX 20K FPGA 652-BGA | Intel / Altera
EP20K400BI652-2V Obsolete
Specification Comparison
| Parameter | EP20K400BI652-2V | EP20K400CB652C9ES |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $84.50 | $195.00 |
| Family | APEX 20K | APEX 20KC |
| Series | APEX 20K (EPLD-based SOPC) | APEX 20KC |
| System Gates | 400,000 | β |
| Logic Elements | 16,640 | β |
| Maximum User I/O | 502 | β |
| Embedded Memory (bits) | 212,992 | β |
| Embedded Memory Blocks | ESBs (Embedded System Blocks) | β |
| Macros (per Mouser listing) | 1664 | β |
| Logic Family | CMOS | β |
| Process Technology | 0.22 ΞΌm | 0.15 Β΅m CMOS |
| Core Supply Voltage (VCCINT) | 2.5 V | β |
| Propagation Delay | 2.5 ns (typical) | β |
| Internal Performance | 200 MHz (speed grade -2) | β |
| Operating Temperature | 0 Β°C to +85 Β°C (industrial, "I") | β |
| Package | 652-ball FineLine BGA (35 Γ 35 mm, 1.27 mm pitch) | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Configuration Interface | JTAG (IEEE 1149.1) / Passive Serial | β |
| Logic Elements / Cells | β | 16640 |
| Total System Gates | β | 400000 |
| Embedded Memory (Bits) | β | 212992 |
| Number of User I/O | β | 488 |
| Number of LABs/CLBs | β | [DATA_NEEDED: LAB count] |
| Number of Logic Array Blocks | β | 1040 |
| Maximum Operating Frequency | β | 250 MHz |
| Core Voltage | β | 1.8 V |
| Operating Temperature Range | β | 0Β°C to +85Β°C (Commercial) |
| Package / Case | β | 652-BGA |
| MSL Level | β | 3 (168 Hours) |
| Packaging | β | Tray |
| Programmability Type | β | In-system programmable (SRAM-based) |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL |
| JTAG (IEEE 1149.1) | β | Yes |
| PLL | β | Yes (4-phase) |