EP20K400CF672C-8 vs EP20K400CF672C8ES Comparison
Detailed side-by-side comparison of EP20K400CF672C-8 by Altera and EP20K400CF672C8ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672C-8 | EP20K400CF672C8ES |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $95.00 | $158.40 |
| Family | APEX 20K | APEX 20KC |
| Logic Elements | 16,640 | β |
| Typical Gates | 400,000 | β |
| Macros | 1,664 | β |
| Maximum User I/O | 488 | 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value] |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | β |
| Package Type | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) | β |
| Core Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | β |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO options] | β |
| Pin-to-Pin Delay (tPD) | 1.78 ns (speed grade -8) | β |
| Speed Grade | -8 | β |
| Temperature Grade (C) | Commercial, 0 Β°C to 85 Β°C | β |
| Process Technology | 0.15 Β΅m all-layer copper CMOS | 0.15 Β΅m CMOS |
| Embedded Memory Type | ESB (RAM / ROM / CAM) | β |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel | β |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | β |
| Mounting Type | Surface Mount (BGA) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified data] |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Series | β | EP20K400 |
| Logic Cells / Macros | β | 16,640 |
| System Gates (typical) | β | 400,000 |
| System Gates (maximum) | β | 212,992 [DATA_NEEDED: confirm datasheet interpretation] |
| Bidirectional I/O | β | 484 |
| Propagation Delay | β | 2.5 ns |
| Maximum Internal Frequency | β | 301.21 MHz |
| Nominal Supply Voltage | β | 1.8 V |
| Supply Voltage Range | β | 1.71 V to 1.89 V |
| Operating Temperature | β | 0Β°C to 85Β°C (Commercial) |
| Package | β | 672-BGA FineLine (FC-FBGA / S-PBGA-B672) |
| Logic Family | β | CMOS |
| Architecture | β | MultiCoreβ’ (LUT + Embedded System Block) |
| Programming Method | β | JTAG / in-system via configuration memory |