EP20K400EBC652-1X vs EP20K400GC655-1 Comparison
Detailed side-by-side comparison of EP20K400EBC652-1X by Intel and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400EBC652-1X | EP20K400GC655-1 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.00 | $135.00 |
| Family | APEX 20KE | APEX 20K |
| Series | APEX-20KEยฎ | EP20K400 |
| Logic Elements / Cells | 16640 | โ |
| System Gates | 1052000 (typical marketing) | โ |
| Embedded Memory (bits) | 212992 | โ |
| Number of Macrocells | 1664 | โ |
| Number of User I/Os | 488 | โ |
| Supply Voltage - Core | 1.8 V (1.71 V to 1.89 V) | โ |
| Supply Voltage - I/O | 2.5 V (multi-voltage I/O supported) | โ |
| Process Technology | 0.22 ยตm CMOS | 0.22 ยตm CMOS |
| Package / Case | 652-BGA (45 x 45 mm) | โ |
| Supplier Device Package | 652-BGA | โ |
| Operating Temperature | 0 ยฐC to +85 ยฐC (Commercial) | 0 ยฐC to +85 ยฐC (commercial) |
| Speed Grade | -1X (faster bin) | โ |
| Mounting Type | Surface Mount | Through-Hole |
| Propagation Delay (per macrocell) | [DATA_NEEDED: per-datasheet ns] | โ |
| RoHS Status | [DATA_NEEDED: not confirmed for this specific lot] | Non-compliant (contains lead in ceramic package) |
| Lead-Free | Yes (per modern distribution) | โ |
| Logic Elements | โ | 16,640 |
| Maximum Gates | โ | 1,052,000 |
| Typical Gates | โ | 400,000 |
| Embedded System Blocks (ESBs) | โ | 4 |
| Total RAM Bits | โ | 212,992 |
| Maximum User I/O | โ | 502 |
| Dedicated Inputs | โ | 6 |
| Core Supply Voltage | โ | 2.5 V |
| I/O Supply Voltage | โ | 3.3 V |
| Maximum Internal Frequency | โ | 250 MHz |
| Propagation Delay | โ | 2.5 ns |
| Package | โ | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin Count | โ | 655 |
| Configuration Modes | โ | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | โ | IEEE 1149.1 (JTAG) |