EP20K400EBC652-1X vs EP20K600CB652C7ES Comparison
Detailed side-by-side comparison of EP20K400EBC652-1X by Intel and EP20K600CB652C7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400EBC652-1X | EP20K600CB652C7ES |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $92.00 | $195.00 |
| Family | APEX 20KE | APEX 20KC |
| Series | APEX-20KEยฎ | โ |
| Logic Elements / Cells | 16640 | โ |
| System Gates | 1052000 (typical marketing) | 600,000 |
| Embedded Memory (bits) | 212992 | โ |
| Number of Macrocells | 1664 | โ |
| Number of User I/Os | 488 | โ |
| Supply Voltage - Core | 1.8 V (1.71 V to 1.89 V) | 1.71 V to 1.89 V (1.8 V nominal) |
| Supply Voltage - I/O | 2.5 V (multi-voltage I/O supported) | โ |
| Process Technology | 0.22 ยตm CMOS | 0.15 ยตm CMOS |
| Package / Case | 652-BGA (45 x 45 mm) | โ |
| Supplier Device Package | 652-BGA | โ |
| Operating Temperature | 0 ยฐC to +85 ยฐC (Commercial) | 0 ยฐC to +85 ยฐC (commercial) |
| Speed Grade | -1X (faster bin) | โ |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Propagation Delay (per macrocell) | [DATA_NEEDED: per-datasheet ns] | โ |
| RoHS Status | [DATA_NEEDED: not confirmed for this specific lot] | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (per modern distribution) | โ |
| Logic Elements | โ | 24,320 |
| Maximum System Gates | โ | 1,053,840 |
| Embedded Memory Bits | โ | 311,296 |
| Embedded System Blocks (ESB) | โ | 26 |
| Maximum User I/O | โ | 488 |
| User I/O (this package) | โ | 488 (652-BGA) |
| Maximum Internal Clock Frequency | โ | 1666.6 MHz |
| Propagation Delay | โ | 1.6 ns |
| Package Type | โ | 652-ball FineLine BGA |
| JEDEC Package Code | โ | S-PBGA-B652 |
| Configuration Modes | โ | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | โ | IEEE 1149.1 compliant |
| PLLs | โ | 4 |