EP20K400FI672-2N vs EP20K400FI672-2 Comparison
Detailed side-by-side comparison of EP20K400FI672-2N by Altera and EP20K400FI672-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoleteSpecification Comparison
| Parameter | EP20K400FI672-2N | EP20K400FI672-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $188.75 | $92.40 |
| Family | APEX 20K | APEX-20K |
| Typical Gates | 400,000 | β |
| Logic Elements / Cells | 16,640 | β |
| Maximum User I/O | 488 | β |
| Embedded Memory Bits | 212,992 bits | 212992 |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count per family datasheet] | β |
| Process Technology | 0.22 Β΅m CMOS | 0.22 Β΅m CMOS |
| Core Voltage | 2.5 V | β |
| Maximum Frequency | 200 MHz | β |
| Package | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) | β |
| Package Body Size | 27 x 27 mm | β |
| Terminal Pitch | 1.0 mm | β |
| Propagation Delay | 3.1 ns | 2.5 ns |
| Speed Grade | -2 | β |
| Operating Temperature | Commercial (0 Β°C to +70 Β°C) [DATA_NEEDED: industrial variant] | 0 Β°C to +85 Β°C (Commercial) |
| Moisture Sensitivity Level (MSL) | 3 | β |
| Peak Reflow Temperature | 220 Β°C | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | Compliant (lead-free) | Lead-free / RoHS Compliant |
| Configuration Modes | PS, PPS, PPA, JTAG | JTAG, Passive Serial, Passive Parallel |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL | β |
| Logic Elements | β | 16640 |
| Maximum Gates | β | 400,000 gates |
| User I/Os | β | 502 |
| Number of Macros | β | 1664 |
| Core Supply Voltage | β | 2.5 V |
| Maximum Internal Frequency | β | 200 MHz |
| Package Type | β | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) |
| PLLs (Phase-Locked Loops) | β | 4 |