EP20K400FI672-2N - APEX 20K 400K Gates FPGA 672-FCBGA | Altera
MPN: EP20K400FI672-2N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $262 | $2,620.00 |
| 100 | $235.5 | $23,550.00 |
| 500 | $209 | $104,500.00 |
| 1,000 | $188.75 | $188,750.00 |
EP20K400FI672-2N Overview
A Field-Programmable Gate Array (FPGA) is a class of programmable logic device (PLD) that combines an array of configurable logic blocks (CLBs), programmable routing channels, and I/O blocks into a single semiconductor die. In the system hierarchy, FPGAs sit above CPLDs and below custom ASICs: they offer higher logic density and richer I/O than CPLDs, and faster time-to-market than ASICs but at higher unit cost and power. APEX 20K was the first Altera family to combine look-up-table (LUT) logic with embedded array blocks (EABs) of dual-port RAM, providing a hybrid LUT-plus-memory architecture that pre-dated the modern ALM/M9K blocks found in later Cyclone and Stratix families.
Key features of the EP20K400FI672-2N include 212,992 typical bits of embedded memory distributed across the EABs, support for LVTTL, LVCMOS, SSTL, and HSTL I/O standards through dedicated I/O element banks, and multi-volt I/O support for interfacing to 1.8 V, 2.5 V, and 3.3 V peripherals. The device supports in-system configuration via passive serial (PS), passive parallel synchronous (PPS), passive parallel asynchronous (PPA), and JTAG-based configuration, allowing flexible boot from EPC configuration PROMs, microcontrollers, or JTAG chains. The 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) package provides 488 usable user I/O channels and excellent thermal performance for high-utilization designs.
The EP20K400FI672-2N is built on a look-up-table fabric combined with dedicated EABs, so each logic element can implement any 4-input Boolean function while EABs deliver synchronous dual-port RAM up to 2,048 bits each. This hybrid LUT/memory architecture was innovative at introduction and remains useful for legacy designs requiring predictable timing closure on memory-rich datapaths (e.g., FIFOs, shift registers, DSP filters) where modern 7-series FPGAs would require larger and more expensive parts. The 0.22 µm process and 2.5 V core result in a typical quiescent power in the 1-2 W range, with maximum power depending on toggle rate and I/O utilization.
Typical applications for the EP20K400FI672-2N include high-density glue logic in telecom line cards, PCI/PCI-X bridge implementations, custom DSP preprocessing for baseband and image pipelines, and ASIC prototyping platforms. It is also frequently used as a bridge between parallel microcontrollers and high-speed serial buses (such as LVDS links) and as a re-programmable controller in industrial automation modules where field firmware updates are required.
When designing with this part, note that the APEX 20K family is now in the legacy/extended-life portfolio. Lead times and stocking are constrained to specialty distributors, and Intel/Altera recommends migration to the Cyclone or MAX series for new designs. Existing users should treat the EP20K400 as a long-term-supported, not-actively-marketed component with stable firmware compatibility via the Quartus II design toolchain (versions 4.0 through 13.0 depending on the specific device variant).
Drop-in alternatives for EP20K400FI672-2N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-2N (same form factor and footprint) — differing in Operating Temperature, Package, Family, Process Technology, Speed Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400FI672-2
✅ Drop-In✓ In Stock
$92.4 / Unit
View Datasheet →EP20K400EFI672-2N
✅ Drop-In✓ In Stock
$105 / Unit
View Datasheet →EP20K400FC672-2
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K400FC672-3
✅ Drop-In✓ In Stock
$138 / Unit
View Datasheet →EP20K400EFC672-2
✅ Drop-In✓ In Stock
$92.75 / Unit
View Datasheet →EP20K400FI672-2N Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Typical Gates | 400,000 |
| Logic Elements / Cells | 16,640 |
| Maximum User I/O | 488 |
| Embedded Memory Bits | 212,992 bits |
| Process Technology | 0.22 µm CMOS |
| Core Voltage | 2.5 V |
| Maximum Frequency | 200 MHz |
| Package | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Package Body Size | 27 x 27 mm |
| Terminal Pitch | 1.0 mm |
| Propagation Delay | 3.1 ns |
| Speed Grade | -2 |
| Moisture Sensitivity Level (MSL) | 3 |
| Peak Reflow Temperature | 220 °C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (lead-free) |
| Configuration Modes | PS, PPS, PPA, JTAG |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL |
EP20K400FI672-2N 27 x 27 mm Pin Configuration Guide
Pin configuration for EP20K400FI672-2N (27 x 27 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FI672-2N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FI672-2N is suitable for 6 applications: Telecom Line-Card Glue Logic, PCI / PCI-X Bridge Implementation, Custom DSP Preprocessing (Baseband / Image), ASIC Prototyping Platform, Industrial Automation Controller, Legacy Interface Bridge (LVDS / Parallel).
Telecom Line-Card Glue Logic
The EP20K400FI672-2N fits telecom line-card glue logic because it offers 400K gates and 488 user I/O in a single BGA package, eliminating the multiple CPLDs typically needed to bridge a network processor to framer, PHY, and timing devices. Its 16,640 logic elements with 200 MHz internal operation handle time-critical backplane protocols such as UTOPIA, POS-PHY, and Serial RapidIO glue. The EAB blocks implement up to 212,992 bits of distributed dual-port RAM for cell buffers and lookup tables without consuming general logic. Compared to a modern Cyclone V, this part consumes roughly 2-3x more power, but for legacy line-card designs already validated against it, the drop-in fit preserves firmware investment.
Recommended
PCI / PCI-X Bridge Implementation
The EP20K400FI672-2N is well suited as a PCI or PCI-X bridge IC because it provides the 488 user I/O required for 64-bit/66 MHz PCI-X buses plus side-band signals, while its 200 MHz fabric delivers comfortable timing margin for the 66 MHz PCI-X clock. Designers implement the bus arbiter, address translation, and FIFO buffering using EAB-based dual-port RAM blocks, which provide deterministic read/write timing without inferring RAM from logic cells. Pin compatibility with EP20K400FC672-2 enables speed-grade migration for timing closure. Engineers porting legacy PCI designs should note that Quartus II 13.0 is the last officially supported toolchain for APEX 20K parts.
Recommended
Custom DSP Preprocessing (Baseband / Image)
The EP20K400FI672-2N supports custom DSP preprocessing for baseband and image pipelines thanks to its 16,640 logic elements and 212,992 EAB memory bits that implement FIR filters, FFT twiddle-factor tables, and pixel line buffers. The 200 MHz fabric clock delivers sufficient throughput for low-MHz baseband samples or VGA-resolution image preprocessing in industrial vision. EAB-based dual-port RAM allows simultaneous read/write access required for pipelined FIR taps without read-before-write hazards. For higher sample rates, designers can scale to multiple APEX 20K parts or migrate to a modern Cyclone V SE5 SoC with dedicated DSP blocks.
Recommended
ASIC Prototyping Platform
The EP20K400FI672-2N works as an ASIC prototyping vehicle because its 400K gates and 488 I/O allow large RTL partitions to be compiled and verified at near-ASIC speeds up to 200 MHz, supporting both single-FPGA prototyping of medium-sized ASIC blocks and multi-FPGA emulation through JTAG scan chains. The 672-pin FC-FBGA package exposes enough I/O to map wide datapath ASIC pins (64-bit, 128-bit buses) without external multiplexing. Existing ASIC IP compiled for APEX 20K re-targets to Cyclone V with Quartus Prime, but the legacy Altera IP library preserves the original timing characteristics when migration is undesirable.
Recommended
Industrial Automation Controller
The EP20K400FI672-2N serves as a re-programmable controller in industrial automation modules because its large gate count supports fieldbus protocol stacks (Profibus, DeviceNet, CANopen) plus motion-control state machines on a single device. The 672-pin FC-FBGA package provides enough I/O for multi-axis encoder inputs, PWM outputs, and parallel sensor buses. In-system configuration via JTAG or EPC PROMs enables remote firmware updates without removing the controller from service. Designers should budget for the 2.5 V core power, which is non-standard in modern industrial designs that prefer 1.2 V or 3.3 V rails.
Recommended
Legacy Interface Bridge (LVDS / Parallel)
The EP20K400FI672-2N bridges legacy parallel microcontrollers to high-speed serial LVDS links because its 488 user I/O can absorb wide parallel buses while its 200 MHz fabric handles LVDS serialization at hundreds of megabits per second. EAB blocks implement elastic buffers between the parallel and serial clock domains, absorbing phase and frequency differences without metastability. The -2 speed grade provides comfortable timing margin for serializer/deserializer (SerDes) bridging in industrial camera link or proprietary backplane links. The same approach is widely used in legacy military and aerospace designs that retain APEX 20K parts for obsolescence management.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-2N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400FI672-2 | EP20K400EFI672-2N | EP20K400FC672-2 | EP20K400FC672-3 | EP20K400EFC672-2 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-pin FC-FBGA | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same | 672-pin FC-FBGA - same |
| Typical Gates | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 |
| Maximum User I/O | 488 | 488 | 488 | 488 | 488 | 488 |
| Speed Grade | -2 | -2 | -2 | -2 | -3 (faster) | -2 |
| Embedded Memory Bits | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 | 212,992 |
| Core Voltage | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Lead-free terminal finish with identical -2 speed grade (vs EP20K400FI672-2)
- Original industrial-temperature rating for harsh environments (vs EP20K400FC672-2)
- Highest-volume stocking part with Rochester Electronics fulfillment (vs EP20K400EFI672-2N)
Design Notes
The 672-pin FC-FBGA package dissipates 1-2 W quiescent power at typical toggle rates, with peak power reaching 3-4 W at 200 MHz with high I/O utilization. The exposed die (flip-chip BGA) provides good thermal conduction to inner board copper planes. Design the PCB with at least 8 inner ground planes directly under the BGA footprint and a continuous thermal via array (0.3 mm pitch) to the bottom side heatsink area. Estimated: with 4 thermal vias at 0.5 mW each, the package thermal resistance θJA can reach approximately 12-15 °C/W, well within the commercial operating range without an external heatsink.
The 672-pin FC-FBGA package has a 1.0 mm ball pitch and 27 x 27 mm body, requiring a 6-layer or 8-layer PCB with microvia (laser-drilled) or via-in-pad construction for reliable breakout routing. Use a high-density interconnect (HDI) stack-up with 1-2-1 or 1-2-1-2-1 layer count to fan out the inner rows of balls. Match trace lengths within ±150 mil for all configuration clock and data signals to meet setup/hold requirements during in-system programming. Recommended: impedance-controlled stack-up with 50 Ω single-ended and 100 Ω differential traces for LVDS pairs.
Do not substitute the EP20K400FI672-2N with a different speed grade without re-running timing closure in Quartus II - the -1 grade is approximately 20% slower than -2, which may break timing paths that meet margin at -2. Also note that the APEX 20K family requires 2.5 V core supply; using a 3.3 V supply will damage the device. Configuration PROMs must be sized for the 16,640 logic element bitstream; EPC16 or larger PROMs are required for typical designs. Always check the device ID via JTAG before in-system programming to confirm the package/device matches the bitstream.
Decouple the EP20K400FI672-2N core and I/O supplies with at least 8 ceramic capacitors (0.1 µF X7R 0402) placed within 5 mm of each power-pin cluster on the FC-FBGA footprint. Add 4 bulk capacitors (10 µF X5R 0805) near the package corners for transient current suppression. Separate analog and digital ground planes if the design uses the LVDS or SSTL I/O standards; join them at a single point under the FPGA to avoid ground-loop noise coupling into the high-speed serial links.
Compliance Information
Lead-free terminal finish per the -N suffix. RoHS and REACH compliance per Altera product page. AEC-Q100 not applicable (FPGA, not automotive-qualified analog IC). Halogen-free and conflict-mineral status not explicitly stated in retrieved data.
