EP20K400FI672-2X vs EP20K400FI672-2 Comparison
Detailed side-by-side comparison of EP20K400FI672-2X by Intel and EP20K400FI672-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoleteSpecification Comparison
| Parameter | EP20K400FI672-2X | EP20K400FI672-2 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $171.00 | $92.40 |
| Family | APEX 20K | APEX-20K |
| Logic Elements | 16,640 | 16640 |
| Typical Gates | 400,000 system gates | β |
| Embedded Memory | 212,992 bits | β |
| User I/O Pins | 496 | β |
| Package | 672-ball BGA (FI672) | β |
| Package Code | BGA | β |
| Terminal Form | Ball | β |
| No. of Terminals | 672 | β |
| Package Shape | Square | β |
| Speed Grade | -2X | β |
| Operating Temperature | -40C to +85C (industrial) | 0 Β°C to +85 Β°C (Commercial) |
| Core Voltage | 1.8 V | β |
| I/O Voltage Support | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) | β |
| Configuration Method | SRAM (serial EPROM or JTAG) | β |
| JTAG Support | Yes (IEEE 1149.1) | β |
| Process Technology | 0.18 um CMOS, 6-metal | 0.22 Β΅m CMOS |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Lead-free / RoHS Compliant |
| Maximum Gates | β | 400,000 gates |
| User I/Os | β | 502 |
| Embedded Memory Bits | β | 212992 |
| Number of Macros | β | 1664 |
| Core Supply Voltage | β | 2.5 V |
| Maximum Internal Frequency | β | 200 MHz |
| Propagation Delay | β | 2.5 ns |
| Package Type | β | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) |
| PLLs (Phase-Locked Loops) | β | 4 |
| Configuration Modes | β | JTAG, Passive Serial, Passive Parallel |
| Mounting Type | β | Surface Mount (BGA) |