EP20K400FI672-2X - 400K Gate APEX 20K FPGA | Intel / Altera
MPN: EP20K400FI672-2X ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $256.5 | $2,565.00 |
| 100 | $228 | $22,800.00 |
| 500 | $199.5 | $99,750.00 |
| 1,000 | $171 | $171,000.00 |
EP20K400FI672-2X Overview
A Field Programmable Gate Array (FPGA) is a type of programmable logic device (PLD) that allows the designer to configure its logic resources, interconnect, and I/O behavior after manufacture. Within the broader programmable logic taxonomy, FPGAs sit alongside CPLDs (Complex Programmable Logic Devices), SPLDs (Simple PLDs), and ASICs (Application-Specific Integrated Circuits). APEX 20K was an early multi-core architecture that combined Look-Up Table (LUT)-based logic elements with embedded system blocks (ESBs) usable as RAM, ROM, or FIFO, allowing designers to build complete systems-on-a-chip on a single FPGA fabric.
The -2X speed grade and industrial temperature rating make the EP20K400FI672-2X suitable for moderate-performance industrial applications requiring guaranteed timing closure across a -40C to +85C operating range. The device is configured via Altera's legacy Quartus II (or MAX+PLUS II) toolchain using SRAM-based configuration memory, typically loaded from a serial configuration EPROM at power-up. MultiVolt I/O support allows interfacing with 1.8V, 2.5V, 3.3V, and 5V devices without external level translation, simplifying board-level integration in mixed-voltage systems.
Key architectural features include a four-level hierarchical interconnect structure with FastTrack routing, dedicated carry chains for high-speed arithmetic, embedded CAM blocks for content-addressable memory, and JTAG (IEEE 1149.1) boundary-scan test support. The device is fabricated in a 0.18 um CMOS process with six layers of metal interconnect, operating from a 1.8V core supply. Per-pin I/O registers and dedicated clock management circuits support high-bandwidth datapath designs typical of communications infrastructure.
Typical applications include telecommunications line cards, network switches and routers, DSP co-processors, high-speed serial protocol bridging (UTOPIA, POS-PHY, RapidIO), video and image processing pipelines, and industrial control systems. The wide I/O count (496 pins) supports many parallel bus interfaces, while the embedded memory enables efficient on-chip FIFO buffering for streaming data.
When designing with this part, ensure proper decoupling (0.1 uF + bulk capacitance per VCC/GND pair), careful power-plane segmentation between the 1.8V core and 3.3V I/O rails, and JTAG chain planning for in-system programming. Note that the APEX 20K family is now legacy / NRND (Not Recommended for New Designs); consider Cyclone, Arria, or Stratix equivalents for new designs unless second-source legacy supply is required.
Drop-in alternatives for EP20K400FI672-2X — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K400FI672-2X (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, RoHS Status, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K400EFI672-2X
✅ Drop-In✓ In Stock
$168 / Unit
View Datasheet →EP20K400FI672-2
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View Datasheet →EP20K400FI672-2V
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$195 / Unit
View Datasheet →EP20K400FI672-2N
✅ Drop-In✓ In Stock
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View Datasheet →EP20K400EFC672-2X
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View Datasheet →EP20K400FG672-2
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$92 / Unit
View Datasheet →EP20K300EFI672-2X
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$171 / Unit
View Datasheet →EP20K400FI672-2X Maximum Ratings & Electrical Characteristics
| Family | APEX 20K |
| Logic Elements | 16,640 |
| Typical Gates | 400,000 system gates |
| Embedded Memory | 212,992 bits |
| User I/O Pins | 496 |
| Package | 672-ball BGA (FI672) |
| Package Code | BGA |
| Terminal Form | Ball |
| No. of Terminals | 672 |
| Package Shape | Square |
| Speed Grade | -2X |
| Operating Temperature | -40C to +85C (industrial) |
| Core Voltage | 1.8 V |
| I/O Voltage Support | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Configuration Method | SRAM (serial EPROM or JTAG) |
| JTAG Support | Yes (IEEE 1149.1) |
| Process Technology | 0.18 um CMOS, 6-metal |
EP20K400FI672-2X square Pin Configuration Guide
Pin configuration for EP20K400FI672-2X (square package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K400FI672-2X.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K400FI672-2X is suitable for 6 applications: Telecommunications Line Cards, Network Switches and Routers, DSP Co-Processor and Front-End Processing, Video and Image Processing Pipelines, Industrial Control Systems, High-Speed Serial Protocol Bridging.
Telecommunications Line Cards
The EP20K400FI672-2X's 496 user I/O pins and 400K system gates make it well-suited for telecom line-card designs requiring wide parallel buses (UTOPIA, POS-PHY) and high logic density. The 212,992 bits of embedded SRAM support on-chip FIFO buffering for ATM, SONET, and Ethernet traffic, while the APEX 20K architecture provides dedicated carry chains for high-speed datapath arithmetic. Industrial temperature rating (-40C to +85C) ensures reliable operation in outdoor cabinet environments. Compared with a discrete ASIC approach, this FPGA allows rapid design iteration while maintaining the throughput required for OC-48 / 2.5 Gbps class line interfaces.
Recommended
Network Switches and Routers
Network switch and router designs leverage the EP20K400FI672-2X for packet-processing engines, queue managers, and table-lookup pipelines. The 16,640 logic elements handle header parsing and classification, while embedded memory blocks implement CAM-like lookup tables for fast routing decisions. The MultiVolt I/O standard allows direct interfacing with 3.3V PHY devices and 5V legacy bus peripherals without external level translation, reducing BOM cost. Combined with JTAG (IEEE 1149.1) support for board-test access, the part is well-matched to enterprise networking hardware.
Recommended
DSP Co-Processor and Front-End Processing
As a DSP co-processor, the EP20K400FI672-2X accelerates FIR filters, FFT engines, and baseband processing blocks in wireless and signal-intelligence systems. Its dedicated carry chains deliver high multiply-accumulate throughput, and the 212,992 bits of embedded SRAM provide coefficient and sample storage close to the logic. The -2X speed grade offers moderate timing margin suitable for sample rates up to ~80 MHz in 16-bit datapaths. The wide 672-ball BGA footprint supports many parallel ADC/DAC interfaces, enabling multi-channel receiver designs.
Recommended
Video and Image Processing Pipelines
The EP20K400FI672-2X implements real-time video processing functions such as scaling, filtering, and color-space conversion in broadcast and surveillance equipment. Its 400K gate capacity handles multi-tap filter architectures, and the 496 I/O pins support wide parallel video buses (24-bit RGB, ITU-R BT.656). The embedded memory blocks implement line buffers and frame-store FIFOs without external SRAM. Industrial temperature rating suits outdoor camera and broadcast head-end installations where -40C to +85C operation is mandatory.
Recommended
Industrial Control Systems
Industrial PLC, motion controller, and SCADA system designs use the EP20K400FI672-2X for high-density glue logic, encoder interfacing, and protocol bridging. The MultiVolt I/O (1.8V-5V) interfaces directly to 5V industrial sensors and 24V-tolerant opto-isolated inputs (with external resistor dividers), while the -40C to +85C rating suits factory-floor and outdoor cabinet deployments. SRAM-based configuration allows field firmware updates via JTAG, simplifying long-life maintenance of installed machinery.
Recommended
High-Speed Serial Protocol Bridging
The EP20K400FI672-2X serves as a flexible bridge between legacy parallel buses and high-speed serial protocols (RapidIO, Utopia, POS-PHY) in storage and telecom systems. Its 400K gate count absorbs protocol-stack overhead plus user-defined glue logic, while the wide I/O count supports 32-bit and 64-bit parallel PHY interfaces. Embedded memory implements packet buffers, and JTAG enables in-system debugging during protocol certification.
Recommended
Recommended Products Summary
Engineering reference data for EP20K400FI672-2X — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K400EFI672-2X | EP20K400FI672-2 | EP20K400FI672-2V | EP20K400FI672-2N | EP20K300EFI672-2X |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 672-ball BGA (FI672) | 672-ball BGA (FI672) - same | 672-ball BGA (FI672) - same | 672-ball BGA (FI672) - same | 672-ball BGA (FI672) - same | 672-ball BGA (FI672) - same |
| Family | APEX 20K | APEX 20KE | APEX 20K | APEX 20K | APEX 20K | APEX 20KE |
| Typical Gates | 400,000 | 400,000 | 400,000 | 400,000 | 400,000 | 300,000 (-25%) |
| Logic Elements | 16,640 | 16,640 | 16,640 | 16,640 | 16,640 | 11,520 |
| Embedded Memory | 212,992 bits | 212,992 bits (higher bandwidth) | 212,992 bits | 212,992 bits | 212,992 bits | 147,456 bits |
| User I/O Pins | 496 | 496 | 496 | 496 | 496 | 488 |
| Speed Grade | -2X | -2X | -2 | -2 | -2 | -2X |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Key Differentiators
- Highest gate density in its APEX 20K family (vs EP20K300EFI672-2X)
- Original APEX 20K architecture (broadest legacy support) (vs EP20K400EFI672-2X)
- Industrial temperature rating with -2X speed grade (vs EP20K400FI672-2 (commercial temp))
Design Notes
The EP20K400FI672-2X requires a 1.8V core supply (VCCINT) with tight regulation: bulk decoupling of 100-330 uF plus 0.1 uF ceramic per VCC pin is recommended. The I/O supply (VCCIO) is independent and can be set to 1.8V, 2.5V, 3.3V, or 5V per bank. Estimated: at typical industrial workloads, core current draw can reach ~1.5 A; a switching DC-DC with adequate bulk filtering is preferred over a linear regulator to minimize dissipation.
The 672-ball BGA package requires careful PCB layout: microvia or via-in-pad technology is recommended for escape routing, with a minimum 4-layer stack-up (signal-GND-power-signal). Match the BGA ball pitch (typically 1.27 mm) to the PCB pad diameter per IPC-7351 guidelines. Power planes should be split cleanly between VCCINT (1.8V) and VCCIO (3.3V) banks to prevent supply coupling, with stitching capacitors placed at every BGA quadrant edge.
Differential pairs (LVDS, HSTL, SSTL) must be length-matched within 50 mil for receiver skew tolerance; the Quartus II fitter reports per-pair skew that should be verified post-place-and-route. Place the configuration EPROM (EPC2 / EPC16) within 2 inches of the FPGA DATA and DCLK pins with series-damping resistors if traces exceed 4 inches. JTAG chain order should place TAPs with the slowest TCK tolerance first.
Common pitfalls: (1) exceeding the 672-ball BGA reflow profile (peak 220C per JEDEC J-STD-020) can damage solder joints; (2) SRAM-based configuration means the design is volatile - an unstable VCCINT at power-up will lose configuration; (3) forgetting to tie nCONFIG, nSTATUS, and CONF_DONE high via 10 kohm pull-ups can prevent boot; (4) the APEX 20K family is NRND - do not commit to it for new designs without sourcing-validation.
Compliance Information
RoHS and REACH compliance not specified in the provided web data; the EP20K400FI672-2V and -2N suffix variants typically indicate Pb-free terminal finishes per Altera/Intel legacy naming conventions. AEC-Q100 does not apply to FPGAs of this class.
