EP20K400FI784-2 vs EP20K400FI784-1 Comparison
Detailed side-by-side comparison of EP20K400FI784-2 by Altera and EP20K400FI784-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400FI784-2 | EP20K400FI784-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $82.40 | $175.00 |
| Device Family | APEX 20K | β |
| Typical Gates | 400,000 | β |
| Logic Elements (LEs) | [DATA_NEEDED: logic elements count] | β |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | β |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count] | β |
| Dedicated Inputs | 4 | 4 |
| Nominal Core Supply Voltage (VCCINT) | 2.5 V | β |
| VCCINT Range | 2.375 V to 2.625 V | β |
| Speed Grade | -2 | β |
| Operating Temperature Range | -40 Β°C to +100 Β°C | β |
| Package Type | S-PBGA-B784 (FineLine BGA) | 784-ball Fine-pitch BGA (S-PBGA-B784) |
| Package Pin Count | 784 balls | β |
| Ball Pitch | 1.000 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | β |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Device Form Factor | Loadable PLD | β |
| Process Technology | [DATA_NEEDED: process node] | 0.18 Β΅m CMOS, 6-layer metal |
| Configuration Memory | SRAM-based (volatile) | β |
| Family | β | APEX 20K |
| Series | β | EP20K400 |
| Device Type | β | Loadable PLD (FPGA-class) |
| Usable Gates | β | 400,000 |
| Logic Elements | β | 1,560 |
| Embedded Memory (EAB RAM) | β | 212,992 bits |
| Maximum User I/O | β | 488 |
| Maximum Internal Clock Frequency | β | 6.1 GHz |
| Operating Junction Temperature | β | -40Β°C to +100Β°C (industrial 'I') |
| Supply Voltage - Core | β | 1.8 V |
| I/O Standards Supported | β | 3.3 V / 5 V PCI, LVTTL, LVCMOS |
| Boundary Scan | β | JTAG IEEE 1149.1 |
| Lead-Free / RoHS | β | [DATA_NEEDED: RoHS status] |