EP20K400GC655-1X vs EP20K400GC655-1 Comparison
Detailed side-by-side comparison of EP20K400GC655-1X by Altera and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-1X | EP20K400GC655-1 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $193.04 | $135.00 |
| Product Family | Altera APEX 20K | β |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Technology | CMOS | β |
| Gate Count | 400K gates | β |
| Logic Elements | 16640 cells | 16,640 |
| Maximum System Frequency | 250 MHz | β |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 2.5 V / 3.3 V | 3.3 V |
| Number of User I/O | 496 | β |
| Number of Dedicated Inputs | 6 | β |
| Number of Terminals | 655 | β |
| Package Type | CPGA-655 (Ceramic Pin Grid Array) | β |
| Package Body Material | Ceramic | β |
| Process Technology | 0.22 um | 0.22 Β΅m CMOS |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| Embedded RAM Bits | [DATA_NEEDED: embedded RAM bits] | β |
| RoHS Status | unknown | Non-compliant (contains lead in ceramic package) |
| Family | β | APEX 20K |
| Series | β | EP20K400 |
| Maximum Gates | β | 1,052,000 |
| Typical Gates | β | 400,000 |
| Embedded System Blocks (ESBs) | β | 4 |
| Total RAM Bits | β | 212,992 |
| Maximum User I/O | β | 502 |
| Dedicated Inputs | β | 6 |
| Maximum Internal Frequency | β | 250 MHz |
| Package | β | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin Count | β | 655 |
| Mounting Type | β | Through-Hole |
| Operating Temperature | β | 0 Β°C to +85 Β°C (commercial) |
| Configuration Modes | β | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |