EP20K400GC655-2N vs EP20K400GC655-1 Comparison
Detailed side-by-side comparison of EP20K400GC655-2N by Altera and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-2N | EP20K400GC655-1 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $127.50 | $135.00 |
| Family | APEX 20KC | APEX 20K |
| Number of Logic Elements | 16640 | β |
| Number of Logic Cells | 16640 | β |
| Total System Gates | 400000 | β |
| Total RAM Bits | 212992 | 212,992 |
| Number of I/O | [DATA_NEEDED: I/O count] | β |
| Number of LABs/CLBs | [DATA_NEEDED: LAB count] | β |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | β |
| I/O Voltage (VCCIO) | 2.5 V (LVDS-capable) | β |
| Process Technology | 0.22 Β΅m CMOS | 0.22 Β΅m CMOS |
| Maximum Operating Frequency | 200 MHz | β |
| Propagation Delay (Tpd) | 3.1 ns | β |
| Package / Case | 655-BCPGA (Ceramic Pin Grid Array) | β |
| Supplier Device Package | 655-CPGA, 62.48 x 62.48 mm | β |
| Operating Temperature | Industrial (per Altera part-number -N suffix) | 0 Β°C to +85 Β°C (commercial) |
| Mounting Type | Through-Hole (CPGA, socket-compatible) | Through-Hole |
| LVDS Support | Yes | β |
| Architecture | MultiCore (LUT + product-term + embedded memory) | β |
| Configuration Method | JTAG / Passive Serial | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead in ceramic package) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Series | β | EP20K400 |
| Logic Elements | β | 16,640 |
| Maximum Gates | β | 1,052,000 |
| Typical Gates | β | 400,000 |
| Embedded System Blocks (ESBs) | β | 4 |
| Maximum User I/O | β | 502 |
| Dedicated Inputs | β | 6 |
| Core Supply Voltage | β | 2.5 V |
| I/O Supply Voltage | β | 3.3 V |
| Maximum Internal Frequency | β | 250 MHz |
| Propagation Delay | β | 2.5 ns |
| Package | β | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin Count | β | 655 |
| Configuration Modes | β | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |