EP20K400GC655-2X vs EP20K400GC655-3 Comparison
Detailed side-by-side comparison of EP20K400GC655-2X by Altera and EP20K400GC655-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GC655-2X | EP20K400GC655-3 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $310.00 |
| Family | APEX 20K | APEX 20K |
| Series | APEX-20KCยฎ | APEX-20KC |
| Logic Elements / Cells | 16640 | โ |
| System Gates | 400000 | โ |
| Total RAM Bits | 212992 | 212992 |
| Number of I/O | 496 | โ |
| Number of Dedicated Inputs | 6 | โ |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | โ |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | โ |
| Maximum Operating Frequency | 200 MHz | โ |
| Process Technology | 0.22 ยตm CMOS | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V | โ |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | โ |
| Package Type | 655-BCPGA (SPGA655) | โ |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | โ |
| Package Dimensions | 47 x 47 mm | โ |
| Peak Reflow Temperature | 220 ยฐC | โ |
| Mounting Type | Through-hole (CPGA) | โ |
| Programmability | In-system, JTAG (IEEE 1149.1) | โ |
| Operating Temperature | [DATA_NEEDED: temperature grade] | -40C to +85C (industrial) |
| RoHS Status | unknown | [DATA_NEEDED: rohs status] |
| Manufacturer | โ | Intel (formerly Altera) |
| Logic Elements | โ | 16640 |
| Number of Gates | โ | 400000 |
| Supply Voltage - Core | โ | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | โ | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | โ | 167 MHz (per FPGAkey) |
| Package / Case | โ | 655-BCPGA |
| Supplier Device Package | โ | 655-CPGA (62.48 x 62.48 mm) |
| Speed Grade | โ | -3 (slowest grade in family) |
| Propagation Delay (tPD) | โ | 3.6 ns (per Microchip USA listing) |
| JTAG Support | โ | IEEE 1149.1 Boundary-Scan |
| Configuration Modes | โ | Passive Serial, Passive Parallel Sync/Async, Active Serial |