EP20K400GC655-3 vs EP20K400GC655-1 Comparison
Detailed side-by-side comparison of EP20K400GC655-3 by Intel and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-3 | EP20K400GC655-1 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $310.00 | $135.00 |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20K | APEX 20K |
| Manufacturer | Intel (formerly Altera) | β |
| Logic Elements | 16640 | 16,640 |
| Total RAM Bits | 212992 | 212,992 |
| Number of Gates | 400000 | β |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | β |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | β |
| Operating Temperature | -40C to +85C (industrial) | 0 Β°C to +85 Β°C (commercial) |
| Maximum Frequency | 167 MHz (per FPGAkey) | β |
| Process Technology | 0.22 um CMOS | 0.22 Β΅m CMOS |
| Package / Case | 655-BCPGA | β |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | β |
| Speed Grade | -3 (slowest grade in family) | β |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | β |
| JTAG Support | IEEE 1149.1 Boundary-Scan | β |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| RoHS Status | [DATA_NEEDED: rohs status] | Non-compliant (contains lead in ceramic package) |
| Maximum Gates | β | 1,052,000 |
| Typical Gates | β | 400,000 |
| Embedded System Blocks (ESBs) | β | 4 |
| Maximum User I/O | β | 502 |
| Dedicated Inputs | β | 6 |
| Core Supply Voltage | β | 2.5 V |
| I/O Supply Voltage | β | 3.3 V |
| Maximum Internal Frequency | β | 250 MHz |
| Propagation Delay | β | 2.5 ns |
| Package | β | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin Count | β | 655 |
| Mounting Type | β | Through-Hole |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |