EP20K400GC655-3 vs EP20K400GC655-2X Comparison
Detailed side-by-side comparison of EP20K400GC655-3 by Intel and EP20K400GC655-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GC655-3 | EP20K400GC655-2X |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $310.00 | $175.00 |
| Series | APEX-20KC | APEX-20KCยฎ |
| Family | APEX 20K | APEX 20K |
| Manufacturer | Intel (formerly Altera) | โ |
| Logic Elements | 16640 | โ |
| Total RAM Bits | 212992 | 212992 |
| Number of Gates | 400000 | โ |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | โ |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | โ |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: temperature grade] |
| Maximum Frequency | 167 MHz (per FPGAkey) | โ |
| Process Technology | 0.22 um CMOS | 0.22 ยตm CMOS |
| Package / Case | 655-BCPGA | โ |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | โ |
| Speed Grade | -3 (slowest grade in family) | โ |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | โ |
| JTAG Support | IEEE 1149.1 Boundary-Scan | โ |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | โ |
| RoHS Status | [DATA_NEEDED: rohs status] | unknown |
| Logic Elements / Cells | โ | 16640 |
| System Gates | โ | 400000 |
| Number of I/O | โ | 496 |
| Number of Dedicated Inputs | โ | 6 |
| Number of LABs/CLBs | โ | [DATA_NEEDED: number of Logic Array Blocks] |
| Number of EABs | โ | [DATA_NEEDED: number of Embedded Array Blocks] |
| Maximum Operating Frequency | โ | 200 MHz |
| Core Supply Voltage | โ | 2.5 V |
| I/O Supply Voltage (MultiVolt) | โ | 2.5 V / 3.3 V / 5 V |
| Package Type | โ | 655-BCPGA (SPGA655) |
| Package Body Material | โ | CERAMIC, metal-sealed cofired grid array |
| Package Dimensions | โ | 47 x 47 mm |
| Peak Reflow Temperature | โ | 220 ยฐC |
| Mounting Type | โ | Through-hole (CPGA) |
| Programmability | โ | In-system, JTAG (IEEE 1149.1) |