EP20K400GC655-3 vs EP20K400GI655-1V Comparison
Detailed side-by-side comparison of EP20K400GC655-3 by Intel and EP20K400GI655-1V by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel
EP20K400GI655-1V β Last Time BuySpecification Comparison
| Parameter | EP20K400GC655-3 | EP20K400GI655-1V |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $310.00 | $155.00 |
| Series | APEX-20KC | β |
| Family | APEX 20K | APEX 20K |
| Manufacturer | Intel (formerly Altera) | β |
| Logic Elements | 16640 | 16,640 |
| Total RAM Bits | 212992 | β |
| Number of Gates | 400000 | β |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | β |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | β |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: industrial vs military grade] |
| Maximum Frequency | 167 MHz (per FPGAkey) | β |
| Process Technology | 0.22 um CMOS | CMOS |
| Package / Case | 655-BCPGA | β |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | β |
| Speed Grade | -3 (slowest grade in family) | β |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | β |
| JTAG Support | IEEE 1149.1 Boundary-Scan | β |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED] |
| Typical Gates | β | 400,000 |
| Maximum User I/O | β | 502 |
| Dedicated Inputs | β | 4 |
| Package Type | β | CBGA-655 (Ceramic Ball Grid Array) |
| Package Code (JESD-30) | β | S-CPGA-P655 |
| Package Equivalence Code | β | SPGA655, 47x47 |
| Propagation Delay | β | 2.5 ns |
| Core Supply Voltage | β | 2.5 V |
| I/O Supply Voltage | β | 2.5 V / 3.3 V |
| Configuration | β | In-system programmable via JTAG |
| Boundary Scan | β | IEEE 1149.1 JTAG |
| MSL Level | β | 1 |
| Package Body Material | β | Ceramic |