EP20K400GI655-1 vs EP20K400GC655-1 Comparison
Detailed side-by-side comparison of EP20K400GI655-1 by Altera and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400GI655-1
EP20K400GI655-1 - 400K Gate APEX 20K FPGA | Altera | 655-BGA
EP20K400GI655-1 ObsoleteIntel
EP20K400GC655-1
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GI655-1 | EP20K400GC655-1 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $135.00 |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | β |
| Technology | CMOS, SRAM-based | β |
| Logic Elements | 16640 | 16,640 |
| Typical Gates | 400000 | 400,000 |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | 6 |
| Total Terminals | 655 | β |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | β |
| JESD-30 Package Code | S-CPGA-P655 | β |
| Operating Temperature | -40C to +85C (Industrial) | 0 Β°C to +85 Β°C (commercial) |
| Moisture Sensitivity Level | MSL 1 | β |
| Peak Reflow Temperature | 220 C | β |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | β |
| Process Node | 0.18 micrometer CMOS | β |
| RoHS Status | Compliant | Non-compliant (contains lead in ceramic package) |
| Series | β | EP20K400 |
| Maximum Gates | β | 1,052,000 |
| Embedded System Blocks (ESBs) | β | 4 |
| Total RAM Bits | β | 212,992 |
| Process Technology | β | 0.22 Β΅m CMOS |
| Core Supply Voltage | β | 2.5 V |
| I/O Supply Voltage | β | 3.3 V |
| Maximum Internal Frequency | β | 250 MHz |
| Package | β | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin Count | β | 655 |
| Mounting Type | β | Through-Hole |
| Configuration Modes | β | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |