EP20K400GI655-1 vs EP20K400GI655-1V Comparison
Detailed side-by-side comparison of EP20K400GI655-1 by Altera and EP20K400GI655-1V by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel
EP20K400GI655-1V β Last Time BuySpecification Comparison
| Parameter | EP20K400GI655-1 | EP20K400GI655-1V |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $155.00 |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | β |
| Technology | CMOS, SRAM-based | β |
| Logic Elements | 16640 | 16,640 |
| Typical Gates | 400000 | 400,000 |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | 4 |
| Total Terminals | 655 | β |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | CBGA-655 (Ceramic Ball Grid Array) |
| JESD-30 Package Code | S-CPGA-P655 | β |
| Operating Temperature | -40C to +85C (Industrial) | [DATA_NEEDED: industrial vs military grade] |
| Moisture Sensitivity Level | MSL 1 | β |
| Peak Reflow Temperature | 220 C | β |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | β |
| Process Node | 0.18 micrometer CMOS | β |
| RoHS Status | Compliant | [DATA_NEEDED] |
| Package Code (JESD-30) | β | S-CPGA-P655 |
| Package Equivalence Code | β | SPGA655, 47x47 |
| Process Technology | β | CMOS |
| Core Supply Voltage | β | 2.5 V |
| I/O Supply Voltage | β | 2.5 V / 3.3 V |
| Configuration | β | In-system programmable via JTAG |
| Boundary Scan | β | IEEE 1149.1 JTAG |
| MSL Level | β | 1 |
| Package Body Material | β | Ceramic |