EP20K400GI655-2 vs EP20K400GI655-1V Comparison
Detailed side-by-side comparison of EP20K400GI655-2 by Altera and EP20K400GI655-1V by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel
EP20K400GI655-1V β Last Time BuySpecification Comparison
| Parameter | EP20K400GI655-2 | EP20K400GI655-1V |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $155.00 |
| Manufacturer | Altera Corporation | β |
| Series | APEX 20K (EP20K400) | β |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Typical Gate Count | 400,000 gates | β |
| Logic Elements (LE) | 16,640 | β |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | β |
| Package | SPGA-655 (47 mm x 47 mm) | β |
| Nominal Supply Voltage | 2.5 V | β |
| Supply Voltage Range | 2.375 V to 2.625 V | β |
| Propagation Delay | 3.1 ns (typical) | 2.5 ns |
| Technology | CMOS SRAM | β |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: industrial vs military grade] |
| Mounting Type | Through-Hole / Socket | β |
| Moisture Sensitivity Level | 1 (per Altera family) | β |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | β |
| Embedded Memory | Embedded System Blocks (ESBs) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Lifecycle Status | Obsolete (legacy Altera APEX 20K family) | β |
| Family | β | APEX 20K |
| Typical Gates | β | 400,000 |
| Logic Elements | β | 16,640 |
| Package Type | β | CBGA-655 (Ceramic Ball Grid Array) |
| Package Code (JESD-30) | β | S-CPGA-P655 |
| Package Equivalence Code | β | SPGA655, 47x47 |
| Process Technology | β | CMOS |
| Core Supply Voltage | β | 2.5 V |
| I/O Supply Voltage | β | 2.5 V / 3.3 V |
| Configuration | β | In-system programmable via JTAG |
| Boundary Scan | β | IEEE 1149.1 JTAG |
| MSL Level | β | 1 |
| Package Body Material | β | Ceramic |