EP20K400GI655-2V vs EP20K400GI655-1 Comparison
Detailed side-by-side comparison of EP20K400GI655-2V by Intel and EP20K400GI655-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GI655-2V | EP20K400GI655-1 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $199.50 | $195.00 |
| Family | APEX 20K | APEX 20K |
| Maximum Gates | 400,000 | β |
| Logic Elements | 16,640 | 16640 |
| Embedded RAM Bits | 212,992 | β |
| User I/O Pins | 496 | β |
| Dedicated Inputs | 6 | 4 |
| Package | SPGA-655 (ceramic, 47 x 47 mm) | β |
| Package Equivalence Code | SPGA655,47X47 | β |
| Process Technology | 0.18 Β΅m CMOS | β |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | β |
| I/O Supply Voltage | 3.3 V | β |
| Propagation Delay | 3.0 ns to 3.1 ns | 2.5 ns |
| Moisture Sensitivity Level (MSL) | 1 | β |
| Package Body Material | Ceramic | β |
| Operating Temperature | Industrial (per -2V speed grade) | -40C to +85C (Industrial) |
| RoHS Status | Non-compliant (ceramic SPGA, contains lead) | Compliant |
| Device Series | β | EP20K400 |
| Technology | β | CMOS, SRAM-based |
| Typical Gates | β | 400000 |
| Maximum User I/O | β | 502 |
| Total Terminals | β | 655 |
| Package Type | β | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | β | S-CPGA-P655 |
| Moisture Sensitivity Level | β | MSL 1 |
| Peak Reflow Temperature | β | 220 C |
| Programmability | β | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | β | 0.18 micrometer CMOS |