EP20K400PI655-2X vs EP20K400GC655-2X Comparison
Detailed side-by-side comparison of EP20K400PI655-2X by Intel and EP20K400GC655-2X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400PI655-2X - APEX 20K 400K Gates FPGA, 655-Pin PQFP | Intel / Altera
EP20K400PI655-2X ObsoleteSpecification Comparison
| Parameter | EP20K400PI655-2X | EP20K400GC655-2X |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $105.00 | $175.00 |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | โ |
| Speed Grade | -2X | โ |
| Maximum Logic Elements | 16,640 | โ |
| Maximum System Gates | 400,000 | โ |
| Maximum RAM Bits | 166,400 | โ |
| Embedded System Blocks (ESBs) | 104 | โ |
| Maximum User I/O Pins | 488 | โ |
| Maximum PLLs | 4 | โ |
| Package | PQFP-655 (Power Quad Flat Pack) | โ |
| Operating Temperature | -40C to +85C (Industrial) | [DATA_NEEDED: temperature grade] |
| Core Voltage | 3.3 V | โ |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | โ |
| Mounting Type | Surface Mount | Through-hole (CPGA) |
| Configuration Method | Serial / Parallel / JTAG | โ |
| Process Technology | 0.18 um CMOS | 0.22 ยตm CMOS |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | โ |
| Lifecycle Status | Obsolete (legacy Altera APEX 20K family) | โ |
| Series | โ | APEX-20KCยฎ |
| Logic Elements / Cells | โ | 16640 |
| System Gates | โ | 400000 |
| Total RAM Bits | โ | 212992 |
| Number of I/O | โ | 496 |
| Number of Dedicated Inputs | โ | 6 |
| Number of LABs/CLBs | โ | [DATA_NEEDED: number of Logic Array Blocks] |
| Number of EABs | โ | [DATA_NEEDED: number of Embedded Array Blocks] |
| Maximum Operating Frequency | โ | 200 MHz |
| Core Supply Voltage | โ | 2.5 V |
| I/O Supply Voltage (MultiVolt) | โ | 2.5 V / 3.3 V / 5 V |
| Package Type | โ | 655-BCPGA (SPGA655) |
| Package Body Material | โ | CERAMIC, metal-sealed cofired grid array |
| Package Dimensions | โ | 47 x 47 mm |
| Peak Reflow Temperature | โ | 220 ยฐC |
| Programmability | โ | In-system, JTAG (IEEE 1149.1) |
| RoHS Status | โ | unknown |