EP20K600CB652C8N vs EP20K600CB652C-8 Comparison

Detailed side-by-side comparison of EP20K600CB652C8N by Altera and EP20K600CB652C-8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C8N EP20K600CB652C-8
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $115.00 $86.00
Family APEX 20KC APEX 20KC (MultiCore)
Device Type Loadable PLD / FPGA β€”
System Gates 600,000 β€”
Logic Elements 24,320 cells 24,320
Embedded Memory 311,296 bits β€”
User I/O Pins 488 β€”
Dedicated Inputs 4 β€”
Outputs 480 β€”
Propagation Delay (typ.) 1.48 ns β€”
Pin-to-Pin Timing 1.78 ns β€”
Internal Frequency (typ.) 301.21 MHz β€”
Core Supply Voltage 1.8 V nominal (1.71 V to 1.89 V) β€”
Process Technology 0.18 Β΅m all-layer copper-metal β€”
Speed Grade C8 -8 (slowest, most timing margin)
Operating Temperature 0 Β°C to 85 Β°C (commercial) 0 C to 85 C (commercial)
Package 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch)
Mounting Type Surface Mount (BGA) Surface Mount (thermally enhanced)
Architecture MultiCore LUT + Embedded System Blocks (ESB) β€”
Pin-Compatible With APEX 20KE family β€”
RoHS Status unknown β€”
Series β€” APEX 20KC
Typical Gates β€” 600,000
Embedded RAM β€” 311,296 bits
User I/Os β€” 488
Propagation Delay β€” 1.48 ns (per published source)
VCCIO Options β€” 1.8 V / 2.5 V / 3.3 V
Process β€” 0.15 Β΅m all-layer copper metal
PCI Compliance β€” PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit
Memory Interface Support β€” DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS
Configuration β€” Enhanced (EPC) bitstream

Datasheets & Resources

Browse All Products Create BOM Request Quote