Altera

EP20K600CB652C-8 - 600K Gates APEX 20KC FPGA, 652-BGA | Altera

MPN: EP20K600CB652C-8 ✗ End of Life

In Stock Ships in 1-3 business days

1.8 V / 2.5 V / 3.3 V Vdss 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch) Package -8 (slowest, most timing margin) Speed DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS Memory

From $86 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$145	$145.00
10	$132	$1,320.00
100	$115	$11,500.00
500	$99.5	$49,750.00
1,000	$86	$86,000.00

ℹ️ All prices are in USD

View Datasheet (PDF) View Alternatives

Quantity

EP20K600CB652C-8 Overview

The Altera EP20K600CB652C-8 is a member of the APEX 20KC family of Field-Programmable Gate Arrays (FPGAs) that integrates up to 600,000 typical gates with 24,320 logic elements, 311,296 RAM bits and 488 user I/Os, fabricated on a 0.15 µm all-layer copper-metal process to deliver up to 35% faster design performance than APEX 20KE devices. It is housed in a thermally enhanced 652-ball LBGA package at 45 x 45 mm with 1.27 mm ball pitch, and uses a -8 speed grade targeting commercial-grade designs.

What is an FPGA? A Field-Programmable Gate Array is a reconfigurable integrated circuit containing an array of programmable logic blocks, interconnect, and I/O cells that the designer configures after manufacturing. The APEX 20KC family sits in Altera's high-density, multi-core hierarchy: logic element -> logic array block -> MegaLAB -> MultiCore architecture -> APEX 20KC device -> PLD family -> programmable semiconductor. APEX 20KC extends APEX 20KE with embedded dual-port RAM and supports LVDS, PCI, PCI-X, DDR SDRAM, ZBT SRAM, and QDR SRAM external memory interfaces.

Key features include 488 user I/Os, 1.48 ns propagation delay per logic element (per published source), VCCIO selectable at 1.8 V, 2.5 V, or 3.3 V for multi-voltage I/O standards, and PCI Local Bus Specification Revision 2.2 compliance at 33 or 66 MHz in 32- or 64-bit widths. The device integrates 311 kbit of embedded memory and supports enhanced configuration (EPC) bitstream loading.

The APEX 20KC architecture combines Look-Up Table (LUT)-based logic, ESBs (Embedded System Blocks) for dual-port SRAM and CAM, and FastTrack interconnect for predictable timing. The -8 speed grade is the slowest (most timing-margin) of the APEX 20KC bin set, giving the longest propagation delay but the lowest cost, often used where timing closure is easy or where designers want additional margin.

Typical applications include telecommunications infrastructure, high-speed image and video processing, industrial control and factory automation, networking line cards, and PCI/PCI-X bridge designs. The wide I/O count and PCI-X support suit designs requiring bus-interface-rich glue logic.

When designing with this device, follow Altera's recommended decoupling scheme for the four VCCINT/VCCIO rail pairs and respect the LBGA thermal pad attach (thermally enhanced package). Configuration bitstream storage (EPC configuration device) and JTAG programming should be planned in the BOM.

This page synthesizes distributor stock, lifecycle status, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.

Drop-in alternatives for EP20K600CB652C-8 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K600CB652C-8 (same form factor and footprint) — differing in Package, Process Technology, Operating Temperature, Device Type, Speed Grade.

EP20K600CB652C7

Altera

Package: 652-ball BGA

Process Technology: 0.15 µm CMOS (all-layer copper interconnect)

Operating Temperature: Commercial (0C to +70C)