EP20K600CB652C8N vs EP20K600CB652C7ES Comparison
Detailed side-by-side comparison of EP20K600CB652C8N by Altera and EP20K600CB652C7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CB652C8N | EP20K600CB652C7ES |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $115.00 | $195.00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | Loadable PLD / FPGA | β |
| System Gates | 600,000 | 600,000 |
| Logic Elements | 24,320 cells | 24,320 |
| Embedded Memory | 311,296 bits | β |
| User I/O Pins | 488 | β |
| Dedicated Inputs | 4 | β |
| Outputs | 480 | β |
| Propagation Delay (typ.) | 1.48 ns | β |
| Pin-to-Pin Timing | 1.78 ns | β |
| Internal Frequency (typ.) | 301.21 MHz | β |
| Core Supply Voltage | 1.8 V nominal (1.71 V to 1.89 V) | β |
| Process Technology | 0.18 Β΅m all-layer copper-metal | 0.15 Β΅m CMOS |
| Speed Grade | C8 | β |
| Operating Temperature | 0 Β°C to 85 Β°C (commercial) | 0 Β°C to +85 Β°C (commercial) |
| Package | 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Architecture | MultiCore LUT + Embedded System Blocks (ESB) | β |
| Pin-Compatible With | APEX 20KE family | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Maximum System Gates | β | 1,053,840 |
| Embedded Memory Bits | β | 311,296 |
| Embedded System Blocks (ESB) | β | 26 |
| Maximum User I/O | β | 488 |
| User I/O (this package) | β | 488 (652-BGA) |
| Supply Voltage - Core | β | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | β | 1666.6 MHz |
| Propagation Delay | β | 1.6 ns |
| Package Type | β | 652-ball FineLine BGA |
| JEDEC Package Code | β | S-PBGA-B652 |
| Configuration Modes | β | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | β | IEEE 1149.1 compliant |
| PLLs | β | 4 |