EP20K600CF672C-7 vs EP20K600CF672C6 Comparison

Detailed side-by-side comparison of EP20K600CF672C-7 by Altera and EP20K600CF672C6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672C-7 EP20K600CF672C6
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $1,620.00 $480.00
Device Family APEX 20KC β€”
Typical Gates 600,000 β€”
Logic Elements 24,576 β€”
Maximum User I/O 508 β€”
Embedded Memory (ESB) 311 kbits β€”
Number of Terminals 672 β€”
Package Type 672-BBGA, FCBGA β€”
Package Dimensions 45 x 45 mm β€”
Ball Pitch 1.27 mm β€”
Process Technology 0.18 Β΅m all-layer copper-metal (APEX 20KC) 0.18 Β΅m CMOS, 6 metal layers
Speed Grade -7 -6 (C6)
Propagation Delay 1.48 ns β€”
Operating Temperature 0 Β°C to 85 Β°C (Commercial) 0 Β°C to +85 Β°C (commercial)
Configuration Interface EPC (Enhanced Configuration) device family β€”
Mounting Type Surface Mount β€”
Lead-Free / RoHS [DATA_NEEDED: lead-free/RoHS status not stated in verified web data] β€”
Family β€” APEX 20KC
Typical Gate Count β€” 600,000 gates
Logic Elements (LEs) β€” 24,320
Embedded System Blocks (ESBs) β€” 160 (each 2,048 bits)
Maximum Embedded RAM β€” 311,296 bits (311 kbit)
Maximum User I/O Pins β€” 508
Package β€” 672-ball FineLine BGA (CF672)
Package Body Size β€” 27 mm Γ— 27 mm
Core Voltage β€” 1.8 V
I/O Standards Supported β€” LVCMOS, LVTTL, HSTL, SSTL, GTL+
Embedded PLLs β€” 4
Configuration Method β€” SRAM-based, JTAG, EPC16/EPC2
RoHS Status β€” Non-RoHS (legacy process)

Datasheets & Resources

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