EP20K600CF672C6 - 600K Gate APEX 20KC FPGA | Altera | BGA-672
MPN: EP20K600CF672C6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $625 | $625.00 |
| 10 | $595 | $5,950.00 |
| 50 | $560 | $28,000.00 |
| 100 | $520 | $52,000.00 |
| 500 | $480 | $240,000.00 |
EP20K600CF672C6 Overview
An APEX 20KC device is a SRAM-based programmable logic device from the broader FPGA (Field-Programmable Gate Array) taxonomy: FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit -> semiconductor. The "20KC" family supports multi-voltage I/O operation, allowing each input/output bank to be independently configured for 1.8V, 2.5V, 3.3V, or 5.0V interfacing, which simplifies mixed-voltage system design.
Key specifications include 508 maximum user I/O pins, an embedded array of 1,536 ESB macrocells, four phase-locked loops (PLLs) for clock management, and a 0.18 µm CMOS process with six metal layers. The "C6" speed grade denotes a commercial-temperature device (0 °C to +85 °C) with a -6 pin-to-pin timing class; the device operates from a 1.8V core supply with separate VCCIO bank supplies.
The architecture pairs a logic array of 24,320 LEs with 160 ESB blocks (each 2,048 bits), giving designers roughly 311 kbit of dual-port SRAM usable as RAM, ROM, or CAM. Four embedded PLLs multiply, divide, and phase-shift incoming clocks with sub-nanosecond jitter, while the APEX I/O ring supports LVCMOS, LVTTL, HSTL, SSTL, and GTL+ standards with slew-rate and drive-strength control.
Typical applications include telecommunications line cards, high-speed data-acquisition front ends, networking bridges, and ASIC prototyping where 600K gates of logic plus embedded memory replace multiple discrete components. The CF672 package (672-ball FineLine BGA, 27 mm × 27 mm body) supports high signal-count designs while remaining socket-compatible across the speed-grade and temperature siblings of the EP20K600 family.
Design considerations include providing a low-noise core 1.8V rail with bulk decoupling, configuring JTAG boundary-scan chains across multi-device boards, and pre-loading configuration bitstreams through a configuration device such as the EPC16 or EPC2. Altera Quartus II (legacy) and MAX+PLUS II provide synthesis and place-and-route support for this device family.
This page consolidates distributor pricing, APEX 20KC family alternatives, and design considerations not found in the original APEX 20KC Family Data Sheet, helping engineers sourcing obsolete or long-lifecycle Altera silicon.
Drop-in alternatives for EP20K600CF672C6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CF672C6 (same form factor and footprint) — differing in Process Technology, Operating Temperature, Speed Grade, Device Type, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672C7
✅ Drop-In✓ In Stock
$2267.89 / Unit
View Datasheet →EP20K600CF672C7ES
✅ Drop-In✓ In Stock
$360 / Unit
View Datasheet →EP20K600CF672C-7
✅ Drop-In✓ In Stock
$1620 / Unit
View Datasheet →EP20K600CF672C-8
✅ Drop-In✓ In Stock
$1150 / Unit
View Datasheet →EP20K600CF672C-9
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP20K600EFC672C7
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP20K600CF672C6 Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Typical Gate Count | 600,000 gates |
| Logic Elements (LEs) | 24,320 |
| Embedded System Blocks (ESBs) | 160 (each 2,048 bits) |
| Maximum Embedded RAM | 311,296 bits (311 kbit) |
| Maximum User I/O Pins | 508 |
| Package | 672-ball FineLine BGA (CF672) |
| Package Body Size | 27 mm × 27 mm |
| Speed Grade | -6 (C6) |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Core Voltage | 1.8 V |
| I/O Standards Supported | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | 4 |
| Process Technology | 0.18 µm CMOS, 6 metal layers |
| Configuration Method | SRAM-based, JTAG, EPC16/EPC2 |
| RoHS Status | Non-RoHS (legacy process) |
EP20K600CF672C6 27 mm × 27 mm Pin Configuration Guide
Pin configuration for EP20K600CF672C6 (27 mm × 27 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K600CF672C6.
Refer to the datasheet for full pin configuration.
Typical Applications
EP20K600CF672C6 is suitable for 6 applications: Telecommunications Line-Card Design, High-Speed Data Acquisition Front End, ASIC Prototyping and Emulation, Networking Bridge and Switch Fabric, Industrial Motion-Control Backplane, Legacy Avionics Display Controller.
Telecommunications Line-Card Design
The EP20K600CF672C6 is well suited to telecom line-card backplanes where 600K gates and 311 kbit of embedded dual-port RAM replace discrete FIFOs, glue logic, and protocol engines. Its 508 user I/Os drive parallel backplane buses or LVTTL/HSTL memories directly, while the four integrated PLLs deskew multiple clocks at 77.76 MHz or 155.52 MHz line rates with sub-nanosecond jitter, critical for TDM and SDH/SONET framer designs. The 1.8V core and banked I/O at 2.5V/3.3V ease mixed-voltage bus interfacing, and the SRAM-based fabric lets carriers field-upgrade firmware across deployed line cards through EPC16/JTAG configuration.
Recommended
High-Speed Data Acquisition Front End
ADC/DAC front-end designs benefit from the EP20K600CF672C6's combination of 24,320 LEs for DSP glue and 311 kbit of dual-port RAM used as elastic buffers between ADC sample clocks and downstream processing clocks. The 508 I/Os accept LVCMOS and LVTTL data from multi-channel ADCs, while four PLLs generate the precise sub-ns-skew clocks that time interleaved converters. Multi-voltage I/O banks let the FPGA sit directly between a 3.3V ADC and a 1.8V DSP ASIC without level shifters, and Quartus II place-and-route closes timing across the 24,320-element array for pipelined FIR/co decimator stages in instrumentation systems.
Recommended
ASIC Prototyping and Emulation
For ASIC prototyping the EP20K600CF672C6 provides 600,000 gates of LUT-based logic plus 311 kbit of embedded SRAM that maps cleanly to register-transfer-level ASIC blocks. Engineers partition ASIC RTL across multiple APEX 20KC devices using the APEX MultiCore interconnect, where the 508 I/Os per package form chip-to-chip buses at LVCMOS/LVTTL speeds. The SRAM-based configuration supports rapid design iteration through EPC16 bitstream reloads, and Quartus II delivers multi-device partitioning with timing-driven place-and-route. This combination made the APEX 20KC family a mainstay of pre-silicon validation in the early 2000s.
Recommended
Networking Bridge and Switch Fabric
Bridging designs between Ethernet, RapidIO, and proprietary backplanes leverage the EP20K600CF672C6's 311 kbit of dual-port SRAM to implement packet FIFOs at line rate, while 24,320 LEs handle header processing and CRC engines. The four PLLs derive the multiple clock domains required for ingress MAC, egress MAC, and switch-fabric cores, with sub-nanosecond jitter suitable for 100/125 MHz GMII/RGMII interfaces. Banked LVCMOS/LVTTL I/Os at 2.5V and 3.3V directly connect PHY devices, and the 672-ball BGA exposes 508 user I/Os sufficient for multi-port bridges without external muxing.
Recommended
Industrial Motion-Control Backplane
In motion-control systems the EP20K600CF672C6 hosts up to 24,320 LEs of PID loop logic, encoder-decoder blocks, and resolver-to-digital converters, with 311 kbit of dual-port RAM holding reference trajectory tables and feedback samples. The four integrated PLLs synchronize encoder sampling, PWM generation, and host communication clocks at sub-ns skew, while 508 user I/Os interface directly to 5V LVTTL drivers via 5.0V-tolerant banks, eliminating external level shifters in 24V/48V industrial environments. The commercial 0-85 °C temperature grade covers most factory-floor enclosures when paired with adequate airflow.
Recommended
Legacy Avionics Display Controller
Avionics display controllers that pre-date DO-254 mandate transitions still rely on the EP20K600CF672C6 for SVGA/XGA graphics generators and ARINC-429 bus interfaces. The 24,320 LEs support frame-buffer address generation and pixel pipelines, while 311 kbit of dual-port RAM acts as double-buffered video memory at 60-85 Hz refresh rates. Multi-voltage I/O banks connect directly to 5V LVTTL frame buffers and 3.3V graphics memory. JTAG boundary-scan via the EPC2 controller enables flight-line firmware updates, and the commercial 0-85 °C grade suits pressurized cabin equipment without modification.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CF672C6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672C7 | EP20K600CF672C-7 | EP20K600EFC672C7 |
|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera |
| Package | 672-ball FineLine BGA (CF672) | 672-ball FineLine BGA (CF672) | 672-ball FineLine BGA (CF672) | 672-ball FineLine BGA (CF672) |
| Family | APEX 20KC | APEX 20KC | APEX 20KC | APEX 20KE |
| Typical Gate Count | 600,000 | 600,000 | 600,000 | 600,000 |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 |
| Embedded RAM | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits |
| Maximum User I/O | 508 | 508 | 508 | 508 |
| Speed Grade | -6 | -7 | -7 | -7 |
| Temperature Grade | Commercial (0 to +85 C) | Commercial (0 to +85 C) | Commercial (0 to +85 C) | Commercial (0 to +85 C) |
| LVDS Support | No | No | No | Yes (APEX 20KE) |
Key Differentiators
- Highest -6 commercial speed grade in the APEX 20KC CF672 family (vs EP20K600CF672C7)
- Massive on-chip dual-port memory for system integration (vs EP20K400FC672-3)
- Four integrated PLLs reduce external clock-tree components (vs EP20K300EFC672-2)
- 508 user I/Os in the CF672 BGA - largest APEX 20KC interface (vs EP20K600CB652C7)
Design Notes
Provide a low-noise 1.8V core rail capable of at least 1.5 A continuous (estimated at 250 mA idle plus dynamic current for ~50% utilization at 100 MHz). Place 330 µF bulk decoupling plus 0.1 µF and 0.01 µF ceramic capacitors within 5 mm of the BGA's core power balls; Altera's APEX 20KC datasheet recommends 4-pin power-pin groups with separate planes for VCCINT, VCCIO, and GND to suppress switching noise into PLLs.
Estimated: at 0.9 W core dissipation in the CF672 27×27 mm FineLine BGA with theta_JA of roughly 12 °C/W, junction-to-ambient rise is about 11 °C, well within the commercial 0-85 °C envelope with adequate airflow. For enclosed enclosures with no airflow, derate by adding a heat spreader or down-bore thermal vias to the inner BGA balls; the EP20K600CF672I7 industrial variant is preferred above 70 °C ambient.
Use a minimum 8-layer PCB stackup with dedicated VCCINT, VCCIO, and ground planes to control impedance of the 508 user I/O traces. The 672-ball FineLine BGA requires 1.27 mm ball pitch and microvia fan-out; 0.20 mm via-in-pad is recommended for the inner rows to escape cleanly. JTAG chain routing must preserve TMS/TDI/TDO 25 kΩ pull-up/-down values per the APEX 20KC datasheet, otherwise ByteBlasterMV configuration can fail intermittently.
Series-terminate LVTTL and LVCMOS outputs to match trace impedance (50 Ω typical for FR-4 microstrips); the APEX 20KC datasheet provides per-bank drive-strength and slew-rate controls (1-24 mA, slow/fast). Clock PLL outputs should be length-matched within 250 mils across all four PLL taps to maintain the sub-ns jitter spec; route PLL supply pins through a ferrite bead to a dedicated filtered 1.8V rail to minimize reference spurs.
Do not migrate bitstreams between APEX 20KC and APEX 20KE without recompiling in Quartus II - although the silicon is pin-compatible, internal ESB and PLL control bits differ. Always regenerate the JEDEC-style .sof or .pof configuration file when swapping FPGA dies; loading a 20KC bitstream into a 20KE part can hang in user mode. Confirm ByteBlasterMV driver version 2.0.0 or newer is installed; legacy parallel-port programming cables fail on modern Windows 10/11 hosts.
Compliance Information
APEX 20KC family devices were originally released under Altera's pre-RoHS lead-bearing process; the verified distributor listings confirm legacy SnPb ball finish. AEC-Q100 is not applicable for industrial-grade FPGAs of this generation. REACH/halogen status not stated in the verified data.
