EP20K600CF672C-7ES vs EP20K600CEF672C7 Comparison
Detailed side-by-side comparison of EP20K600CF672C-7ES by Altera and EP20K600CEF672C7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF672C-7ES | EP20K600CEF672C7 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $2,050.00 | $98.40 |
| Family | APEX 20KC | APEX 20KC (Enhanced Configuration) |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA / Loadable PLD |
| Maximum System Gates | 1,560,000 (typical 600K application gates) | β |
| Typical Logic Elements | 24,320 (per APEX 20KC 600K family) | β |
| Maximum User I/O | 488 | β |
| Total I/O Lines | 504 (per Microchip USA listing) | β |
| Total Inputs | 508 | β |
| Embedded System Blocks (ESBs) | 248 | β |
| Embedded RAM | 248 Kbits (dual-port) | β |
| PLLs | 4 | β |
| Propagation Delay | 1.48 ns to 1.6 ns | 1.48 ns (typ) |
| Maximum Clock Frequency | 1666.6 MHz | β |
| Speed Grade | -7 | β |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 Β΅m CMOS, all-layer copper |
| Package | 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA (FC-FBGA) |
| Operating Temperature | 0 C to 85 C (Commercial) | 0 Β°C to +85 Β°C (commercial) |
| Core Voltage | 1.8 V (typical APEX 20KC, exact value per datasheet) | β |
| Configuration Mode | EPC serial / JTAG IEEE 1149.1 | β |
| Compliance | RoHS status unknown (verify with manufacturer datasheet) | β |
| Manufacturer | β | Intel (formerly Altera) |
| Series | β | APEX 20KC |
| Logic Elements / Cells | β | 24,320 |
| Gate Count (typical) | β | 600,000 gates |
| Maximum Operating Frequency | β | 375.94 MHz |
| User I/Os | β | 488 |
| Core Supply Voltage | β | 1.8 V |
| Package Code | β | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration | β | SRAM-based, serial or parallel (EPC) |
| Embedded Memory | β | EAB blocks (dual-port RAM with byte enables) |
| LVDS Support | β | True-LVDS channels integrated |
| MultiVolt I/O | β | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | β | DDR SDRAM, QDR SRAM |
| JTAG Support | β | IEEE 1149.1 boundary-scan |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |