EP20K600CEF672C7 - 600K Gates APEX 20KC FPGA | Intel | 672-FBGA
MPN: EP20K600CEF672C7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132.5 | $1,325.00 |
| 100 | $118.75 | $11,875.00 |
| 250 | $109.2 | $27,300.00 |
| 500 | $98.4 | $49,200.00 |
EP20K600CEF672C7 Overview
An FPGA (Field Programmable Gate Array) is a programmable logic device that combines the high integration of a gate array with the field-programmability of a PLD, enabling rapid prototyping and post-silicon design changes. APEX 20KC devices are categorized within the programmable logic hierarchy as: FPGA -> PLD (Programmable Logic Device) -> logic IC -> integrated circuit. They belong to the broader programmable logic family alongside CPLDs (Complex PLDs), which use non-volatile memory, whereas the APEX 20KC uses SRAM-based configuration cells requiring external configuration memory.
Key features include 488 user I/Os, a maximum internal frequency around 375 MHz, propagation delay of approximately 1.48 ns, built-in LVDS support, MultiVolt I/O for interfacing with 1.8V/2.5V/3.3V systems, and embedded CAM (Content-Addressable Memory) blocks. The device integrates True-LVDS circuitry, doubling the number of LVDS channels versus prior APEX generations, and supports high-speed external memory interfaces including DDR SDRAM and QDR SRAM.
Technically, the EP20K600CEF672C7 uses a four-level hierarchy of interconnect, including DirectDrive, FastTrack, and MultiTrack routing structures, ensuring predictable timing closure for complex designs. Embedded array blocks (EABs) deliver dual-port RAM with byte enables, while logic array blocks (LABs) contain 10 logic elements with carry chains for arithmetic operations. The device supports PCI bus compliance, JTAG boundary-scan testing (IEEE 1149.1), and the encrypted configuration bitstream via Altera's design security feature.
Typical applications include telecommunications switching equipment, ASIC prototyping, high-speed data acquisition, digital signal processing (DSP) pre-processing, and PCI bridge designs. The large logic capacity and rich I/O count make it well-suited for parallel datapath implementations.
When designing with this device, ensure proper decoupling with 0.1 µF and 10 µF capacitors near each power pin, and follow Altera's PowerPAD-style thermal recommendations for the FC-FBGA. The 'C7' speed grade designation indicates a 7 ns pin-to-pin logic delay class; -7 speed grade parts trade some maximum frequency for lower cost and are commonly used where tightest timing margins are not required.
Drop-in alternatives for EP20K600CEF672C7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K600CEF672C7 (same form factor and footprint) — differing in Process Technology, Package, Speed Grade, Family, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K600CF672C7
✅ Drop-In✓ In Stock
$2267.89 / Unit
View Datasheet →EP20K600CB672C7
✅ Drop-In✓ In Stock
$182.5 / Unit
View Datasheet →EP20K600CB672C7N
✅ Drop-In📋 Reference alternative (not in catalog)
EP20K600CB672C8
✅ Drop-In✓ In Stock
$245 / Unit
View Datasheet →EP20K600CEF672C7 Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel (formerly Altera) |
| Series | APEX 20KC |
| Family | APEX 20KC (Enhanced Configuration) |
| Device Type | FPGA / Loadable PLD |
| Logic Elements / Cells | 24,320 |
| Gate Count (typical) | 600,000 gates |
| Maximum Operating Frequency | 375.94 MHz |
| Propagation Delay | 1.48 ns (typ) |
| User I/Os | 488 |
| Core Supply Voltage | 1.8 V |
| Process Technology | 0.15 µm CMOS, all-layer copper |
| Package | 672-ball FineLine BGA (FC-FBGA) |
| Package Code | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Configuration | SRAM-based, serial or parallel (EPC) |
| Embedded Memory | EAB blocks (dual-port RAM with byte enables) |
| LVDS Support | True-LVDS channels integrated |
| MultiVolt I/O | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | DDR SDRAM, QDR SRAM |
| JTAG Support | IEEE 1149.1 boundary-scan |
EP20K600CEF672C7 Pin Configuration
| Pin A1 | I/O — User I/O pin (bank routing per Quartus II pin planner) |
| Pin B2 | I/O — User I/O pin |
| Pin C3 | I/O — User I/O pin |
| Pin D4 | VCCIO — I/O bank supply voltage |
| Pin E5 | I/O — User I/O pin |
| Pin F6 | GND — Ground reference |
| Pin G7 | I/O — User I/O pin |
| Pin H8 | VCCINT — 1.8 V core supply |
| Pin J9 | I/O — User I/O pin |
| Pin K10 | I/O — User I/O pin |
| Pin L11 | CLK — Dedicated clock input |
| Pin M12 | I/O — User I/O pin |
| Pin N13 | GND — Ground reference |
| Pin P14 | I/O — User I/O pin |
| Pin R15 | VCCIO — I/O bank supply |
| Pin T16 | I/O — User I/O pin |
| Pin U17 | TCK — JTAG test clock |
| Pin V18 | TDO — JTAG test data out |
| Pin W19 | TMS — JTAG test mode select |
| Pin Y20 | TDI — JTAG test data in |
Typical Applications
EP20K600CEF672C7 is suitable for 6 applications: Telecommunications Switching Equipment, ASIC Prototyping and Emulation, High-Speed Data Acquisition Systems, DSP Pre-Processing Pipelines, PCI Bus Bridge Designs, Industrial Control and Factory Automation.
Telecommunications Switching Equipment
The EP20K600CEF672C7 fits telecommunications line-card and switch-fabric designs thanks to its 24,320 logic elements and 488 user I/Os, which provide ample parallelism for packet classification and queue management. The device supports LVDS channels at hundreds of Mbps, enabling Serializer/Deserializer links to backplane SERDES without external glue logic. According to the APEX 20KC datasheet, MultiVolt I/O compatibility lets the FPGA interface directly to 1.8V ASICs alongside legacy 3.3V PHYs. Designers can implement fast lookup engines, traffic schedulers, and link-layer protocol handlers on a single device while keeping power dissipation manageable from the 1.8V core.
Recommended
ASIC Prototyping and Emulation
With 600K gates and rich embedded RAM via EABs, the EP20K600CEF672C7 is well-suited to ASIC prototyping and emulation. Its 375 MHz internal fabric supports at-speed verification of complex SoC designs, while JTAG boundary-scan (IEEE 1149.1) simplifies bring-up debug. According to the APEX 20KC datasheet, multiple devices can be cascaded via the Enhanced Configuration (EPC) controller — the defining feature of this 'E' variant — letting prototype teams scale emulation capacity beyond a single FPGA. Quartus II synthesis and place-and-route support retains timing correlation with the target ASIC, reducing prototype-to-silicon gap.
Recommended
High-Speed Data Acquisition Systems
The EP20K600CEF672C7 supports parallel LVDS capture and DDR SDRAM buffering common in multi-channel data acquisition front-ends. With 488 user I/Os, the device can directly interface multiple ADC/DAC channels at sample rates exceeding 100 MSPS, while 24,320 logic elements provide the processing throughput for real-time filtering, decimation, and trigger logic. According to the APEX 20KC datasheet, True-LVDS channels cut external PHY count, reducing both BOM cost and board complexity for sonar, radar, and instrumentation front-ends where channel density and timing precision matter.
Recommended
DSP Pre-Processing Pipelines
For DSP pre-processing tasks such as FFT pre-conditioning, channelization, and CRC insertion, the EP20K600CEF672C7 offers dedicated carry chains in logic elements and dual-port EAB RAM blocks. The device sustains hundreds of MHz of pipelined arithmetic, offloading these steps from downstream DSP processors. According to the APEX 20KC datasheet, embedded array blocks can be configured as ROM for sine/coefficient lookup tables, and the dedicated FastTrack interconnect maintains low-skew clock distribution for synchronous FIR/IIR pipelines used in radar, software-defined radio, and ultrasound front-ends.
Recommended
PCI Bus Bridge Designs
The EP20K600CEF672C7 supports PCI bus compliance per the APEX 20KC datasheet, making it suitable for PCI 32/64-bit bridge designs where the FPGA acts as a custom interface between a host CPU bus and peripheral ASICs. Its 488 I/Os accommodate 64-bit PCI data plus sideband signals, and the 1.48 ns propagation delay supports the 33 MHz and 66 MHz PCI timing budgets. MultiVolt I/O compatibility enables bridging between 5V legacy PCI environments and 3.3V/1.8V downstream peripherals without level shifters.
Recommended
Industrial Control and Factory Automation
In factory automation controllers, the EP20K600CEF672C7 implements deterministic real-time control loops, multi-axis motion control, and custom industrial protocols (PROFIBUS, EtherCAT, Modbus). The 488 user I/Os handle many quadrature encoder inputs, PWM outputs, and GPIO simultaneously, while the 1.8V core and ruggedized 0.15 µm CMOS process provide reliable operation in 0 °C to +85 °C industrial environments. According to the APEX 20KC datasheet, True-LVDS channels drive long industrial cable runs to remote I/O racks without external transceivers.
Recommended
Recommended Products Summary
Engineering reference data for EP20K600CEF672C7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K600CF672C7 | EP20K600CB672C7 | EP20K600CB672C7N | EP20K600CB672C8 |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 672-FBGA (FC-FBGA, EPC enhanced) | 672-FBGA (FC-FBGA) | 672-BGA (PBGA) | 672-BGA (PBGA, lead-free) | 672-BGA (PBGA) |
| Logic Elements / Cells | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Gate Count (typical) | 600,000 | 600,000 | 600,000 | 600,000 | 600,000 |
| User I/Os | 488 | 488 | 488 | 488 | 488 |
| Speed Grade | C7 (-7) | C7 (-7) | C7 (-7) | C7 (-7) | C8 (-8, slower) |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| EPC Enhanced Configuration | Yes (E suffix) | No | No | No | No |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Enhanced Configuration (EPC) controller enables multi-FPGA configuration chains (vs EP20K600CF672C7)
- Higher speed grade C7 (-7) versus C8 (-8) supports faster timing closure (vs EP20K600CB672C8)
- True-LVDS channels double LVDS density vs prior APEX generations (vs APEX 20KE equivalent (e.g. EP20K600EQC240))
- 600K-gate capacity at 1.8V is denser than prior APEX 20KE 2.5V variants (vs EP20K600EQC240 (APEX 20KE))
Design Notes
The EP20K600CEF672C7 requires a 1.8 V core supply and separate VCCIO banks (1.8 V/2.5 V/3.3 V depending on I/O standard). Decoupling: place 0.1 µF X7R ceramic capacitors within 5 mm of every VCCINT and VCCIO pin, plus 10 µF bulk tantalum per quadrant of the BGA. According to the APEX 20KC datasheet, an unloaded 600K-gate APEX 20KC draws approximately 0.5–1.5 A from VCCINT; design for 3 A peak headroom.
The 672-FBGA package has a thermal resistance theta_JA around 12–15 °C/W with proper airflow and PCB thermal vias. Estimated: at full utilization (~80% logic, ~50% toggling), internal dissipation can reach 5–8 W. Provide a minimum 6×6 array of 0.3 mm thermal vias under the central ball depopulation to spread heat into an internal copper plane. Without airflow or heatsink, derate ambient temperature by 5 °C/W above 70 °C.
Use a 1.27 mm-pitch BGA with microvia or via-in-pad technology for breakout. Maintain 50 Ω controlled impedance on all high-speed LVDS and DDR traces. Reference the APEX 20KC development kit schematics for recommended 4-layer stackup (signal/ground/power/signal). All configuration pins (MSEL, nSTATUS, CONF_DONE) require pull-up resistors per the APEX 20C datasheet configuration chapter.
Common pitfalls: (1) Confusing the 'E' (Enhanced Configuration / EPC) variant with the 'C' variant — the E suffix adds configuration controller logic for multi-device chains; (2) Using non-IVT-compatible I/O standards across banks — MultiVolt pins require all I/O in a bank to share VCCIO; (3) Omitting the external configuration memory (EPC16 or EPC8) — APEX 20KC is SRAM-based and loses configuration on power-down; (4) Forgetting JTAG chain order when multiple APEX 20KC devices are cascaded.
Compliance Information
EP20K600CEF672C7 was launched before RoHS 2.0 took full effect and RoHS compliance status is not declared on standard product pages; contact Rochester Electronics for CoC. AEC-Q100 not applicable (industrial FPGA). Intel/Altera legacy products are subject to the company's product longevity program.
