EP20K600CF672C-9 vs EP20K600CF672C-7ES Comparison

Detailed side-by-side comparison of EP20K600CF672C-9 by Altera and EP20K600CF672C-7ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672C-9 EP20K600CF672C-7ES
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $171.00 $2,050.00
Device Type FPGA (APEX 20KC family, complex PLD) Field Programmable Gate Array (FPGA)
Typical Gate Count 600,000 gates β€”
Logic Elements (LEs) [DATA_NEEDED: logic element count] β€”
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count and total RAM bits] 248
User I/Os 488 pins β€”
PLLs 4 4
Package 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch
Pin Count 672 β€”
Core Supply Voltage (VCCINT) 1.8 V β€”
I/O Supply Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) β€”
Propagation Delay 1.48 ns 1.48 ns to 1.6 ns
Operating Temperature 0 Β°C to +85 Β°C (commercial) 0 C to 85 C (Commercial)
Speed Grade -9 -7
Process Technology 0.15 Β΅m all-layer copper interconnect 0.15 micron all-layer copper CMOS
Configuration Interface Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) β€”
Mounting Type Surface Mount (BGA) β€”
RoHS Status unknown β€”
Family β€” APEX 20KC
Maximum System Gates β€” 1,560,000 (typical 600K application gates)
Typical Logic Elements β€” 24,320 (per APEX 20KC 600K family)
Maximum User I/O β€” 488
Total I/O Lines β€” 504 (per Microchip USA listing)
Total Inputs β€” 508
Embedded RAM β€” 248 Kbits (dual-port)
Maximum Clock Frequency β€” 1666.6 MHz
Core Voltage β€” 1.8 V (typical APEX 20KC, exact value per datasheet)
Configuration Mode β€” EPC serial / JTAG IEEE 1149.1
Compliance β€” RoHS status unknown (verify with manufacturer datasheet)

Datasheets & Resources

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