Altera

EP20K600CF672C-9 - 600K Gates APEX 20KC FPGA 488 I/O BGA-672 | Altera

MPN: EP20K600CF672C-9 ✗ End of Life

In Stock Ships in 1-3 business days

1.8 V Vdss 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) Package -9 Speed

From $171 USD / Unit

MOQ: 1 |

Price updated: 2026-09-07

Volume Pricing

Qty	Unit Price	Extended
1	$285	$285.00
10	$256.5	$2,565.00
100	$228	$22,800.00
500	$199.5	$99,750.00
1,000	$171	$171,000.00

ℹ️ All prices are in USD

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EP20K600CF672C-9 Overview

The Altera EP20K600CF672C-9 is a member of the APEX 20KC family of programmable logic devices, delivering up to 600,000 typical gates of logic integration in a 672-ball fine-pitch BGA (FBGA) package. It is fabricated on a 0.15 µm all-layer copper interconnect process and is targeted at high-performance, high-density data-path and control-path designs. The device is configured at system power-up via a serial data stream from an Altera EPC16, EPC8, EPC4, EPC2, or EPC1 configuration device and supports in-system programmability (ISP) plus one-time programmable (OTP) modes.

What is an FPGA? An FPGA (Field-Programmable Gate Array) is a semiconductor IC containing an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that the designer can wire up after manufacture to implement arbitrary digital logic. APEX 20KC sits in the combined CPLD/FPGA hybrid category historically called "complex PLD" — its LUT-based MegaLAB structure combines coarse-grained PLD-style logic blocks with fine-grained FPGA-style routing. In the broader taxonomy, APEX 20KC belongs to: FPGA > programmable logic > logic IC > integrated circuit > semiconductor.

Key features of the EP20K600CF672C-9 include 30,560 logic elements (LEs), 488 user I/O pins, 1.8 V VCCINT core supply, and MultiVolt I/O supporting 1.8 V, 2.5 V, 3.3 V, and 5.0 V VCCIO levels. The device integrates embedded system blocks (ESBs) for RAM and ROM, four phase-locked loops (PLLs) for clock synthesis, and a four-level hierarchical interconnect structure built on copper metal for high performance. Speed grade -9 places this part in Altera's mid-tier performance bin for the APEX 20KC family.

The APEX 20KC architecture combines LUT-based logic with a high-speed interconnect fabric and dedicated multiplier/ESB blocks, giving designers a single-chip solution for datapath, control logic, and memory functions. The -9 speed grade and the four embedded PLLs support designs with tight clock-to-output budgets and complex clock trees typical of communications and image-processing pipelines.

Typical applications include telecommunications line cards, image and video processing hardware, DSP co-processing engines, high-speed data-acquisition front ends, and ASIC prototyping. The MultiVolt I/O also makes the device useful as a glue-logic bridge between legacy 5 V peripherals and modern 1.8 V / 3.3 V ASICs/CPUs.

When designing with this device, ensure that VCCINT is ramped cleanly to 1.8 V before configuration begins and that the chosen EPC16/EPC8/EPC4 configuration device matches the desired ISP or OTP mode. Decoupling follows the standard APEX 20KC guideline: at least one bulk 33 µF plus one 0.1 µF ceramic per VCCIO bank and a similar network on VCCINT and VCCPD.

This page synthesizes distributor pricing, APEX 20KC family drop-in variants, and practical configuration/PCB guidance that is not available in any single manufacturer datasheet or distributor product page.

Drop-in alternatives for EP20K600CF672C-9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Variants in this series

Same-series models that are drop-in compatible with EP20K600CF672C-9 (same form factor and footprint) — differing in Process Technology, Speed Grade, Package, Operating Temperature, Device Type.

EP20K600CB672C7

Altera

Process Technology: 0.15 µm all-layer copper-metal CMOS

Speed Grade: C7 (commercial, 0 °C to 85 °C)

Package: 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch)