EP20K600CF672C7N vs EP20K600CF672C6 Comparison

Detailed side-by-side comparison of EP20K600CF672C7N by Altera and EP20K600CF672C6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672C7N EP20K600CF672C6
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $108.00 $480.00
Device Family APEX 20KC β€”
Maximum System Gates 1,052,000 β€”
Typical Gates 600,000 β€”
Logic Elements / Cells 24,320 β€”
Maximum User I/O Pins 488 508
Total Package Pins 652 β€”
Package FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch 672-ball FineLine BGA (CF672)
Core Voltage 1.8 V 1.8 V
Maximum Operating Frequency 375.94 MHz β€”
Propagation Delay 1.48 ns β€”
Process Technology 0.15 Β΅m all-layer copper-metal CMOS 0.18 Β΅m CMOS, 6 metal layers
Architecture MultiCore (LUT + Embedded System Memory) β€”
Operating Temperature 0 Β°C to +85 Β°C (Commercial) 0 Β°C to +85 Β°C (commercial)
Speed Grade C7 -6 (C6)
Seated Height 3.50 mm β€”
Mounting Type Surface Mount (BGA) β€”
RoHS Status unknown Non-RoHS (legacy process)
Family β€” APEX 20KC
Typical Gate Count β€” 600,000 gates
Logic Elements (LEs) β€” 24,320
Embedded System Blocks (ESBs) β€” 160 (each 2,048 bits)
Maximum Embedded RAM β€” 311,296 bits (311 kbit)
Package Body Size β€” 27 mm Γ— 27 mm
I/O Standards Supported β€” LVCMOS, LVTTL, HSTL, SSTL, GTL+
Embedded PLLs β€” 4
Configuration Method β€” SRAM-based, JTAG, EPC16/EPC2

Datasheets & Resources

Browse All Products Create BOM Request Quote