EP20K600CF672I8 vs EP20K600CF672I7N Comparison
Detailed side-by-side comparison of EP20K600CF672I8 by Altera and EP20K600CF672I7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF672I8 | EP20K600CF672I7N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $232.00 |
| Family | APEX 20KC | APEX 20KC |
| Device Type | SPLD / FPGA | β |
| Logic Elements / Cells | 24,320 | β |
| Macros (Logic Cells) | 2432 | β |
| Typical Gate Count | 600,000 gates | β |
| Embedded Memory | 311,296 bits | β |
| User I/Os | 488 to 508 | β |
| Number of Pins | 652 (functional) / 672 (BGA balls) | β |
| Propagation Delay (typical) | 1.48 ns | 1.6 ns |
| Internal Frequency (max) | [DATA_NEEDED: max internal frequency in MHz] | β |
| Core Supply Voltage | 1.8 V | β |
| Process Technology | 0.15 Β΅m all-layer copper | β |
| Operating Temperature | 0 Β°C to +85 Β°C (Industrial) | β |
| Package Type | 672-ball BGA, 45 x 45 mm, 1.27 mm pitch | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | Compliant per legacy product records | [DATA_NEEDED: RoHS compliance] |
| Configuration Interface | JTAG / Passive Serial | β |
| Design Tool | Quartus II (legacy MAX+PLUS II) | β |
| Technology | β | 0.15 Β΅m CMOS |
| Maximum System Gates | β | 600,000 |
| Logic Elements | β | 24,320 |
| Maximum User I/O Pins | β | 508 |
| Maximum Internal Frequency | β | 376 MHz |
| Embedded System Blocks (ESBs) | β | 160 |
| Total Embedded RAM (max) | β | 311,296 bits |
| Core Voltage (VCCINT) | β | 1.8 V |
| I/O Voltage (VCCIO) | β | 2.5 V / 3.3 V (MultiVolt, bank-dependent) |
| Package | β | 672-ball FineLine BGA (FC-FBGA) |
| Ball Pitch | β | 1.0 mm |
| Package Body Size | β | 27 mm Γ 27 mm |
| Speed Grade | β | I7 (-40 Β°C to +100 Β°C industrial) |
| Configuration Method | β | JTAG (IEEE 1149.1) + EPC configuration device |
| Lead-Free Finish (N suffix) | β | Yes |