EP20K600CF672I8N vs EP20K600CF672I9N Comparison

Detailed side-by-side comparison of EP20K600CF672I8N by Intel and EP20K600CF672I9N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672I8N EP20K600CF672I9N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $138.00 $120.00
Device Family APEX 20KC β€”
Device Type SPLD / PLD (FPGA-class) β€”
System Gates 600K β€”
Logic Elements / Cells 24,320 β€”
Maximum User I/O (digchip) 488 β€”
Maximum User I/O (Altera) 508 β€”
Total Package Pins 672 β€”
Package Type FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch β€”
Internal Performance 301.21 MHz β€”
Propagation Delay 1.48 ns β€”
Core Supply Voltage 1.8 V β€”
Process Technology 0.15-um all-layer copper-metal 0.15 Β΅m CMOS
Operating Temperature 0C to 85C (Industrial) -40 Β°C to +85 Β°C (industrial)
Pin-Compatible With APEX 20KE family β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Family β€” APEX 20KC
Logic Elements β€” 24,320 cells
Typical Gates β€” 600,000
Maximum Frequency β€” 250 MHz
Core Voltage (VCCINT) β€” 1.8 V
I/O Voltage (VCCIO) β€” [DATA_NEEDED: VCCIO range]
Embedded Memory β€” 311,040 bits (approx. 38 KB)
Package β€” 672-ball FC-FBGA
PLL Count β€” [DATA_NEEDED: PLL count]
User I/O Pins β€” [DATA_NEEDED: max user I/O]
Configuration Mode β€” JTAG / Serial / Parallel
Programming Interface β€” IEEE 1149.1 JTAG

Datasheets & Resources

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