EP20K60EFC144-2 vs EP20K30EFC144-1N Comparison
Detailed side-by-side comparison of EP20K60EFC144-2 by Altera and EP20K30EFC144-1N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K60EFC144-2 | EP20K30EFC144-1N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.75 | $125.00 |
| Series | APEX-20K | APEX-20KE |
| Family | APEX-20KE (Enhanced, 1.8 V core) | β |
| Typical Gates | 60,000 | β |
| Logic Elements | 2,560 | 1,200 |
| Total RAM Bits | 32,768 | β |
| User I/O | 92 to 93 | β |
| Core Supply Voltage | 1.71 V to 1.89 V | β |
| Internal Frequency (max) | 160 MHz | 160 MHz |
| Propagation Delay | 1.72 ns | 1.68 ns |
| Process Technology | 0.18 Β΅m CMOS | β |
| Package | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) | β |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) | 0 Β°C to 85 Β°C (commercial, N suffix) |
| Mounting Type | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 boundary scan | β |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | β |
| Configuration Method | Serial/Parallel passive, JTAG, EPC companion | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Unknown - not stated in verified sources |
| Device Family | β | APEX-20K MultiCore (LUT + Product-Term + ESB) |
| Gates | β | 30,000 |
| Embedded SRAM Bits | β | 24,576 |
| User I/Os | β | 93 (per Mouser/Kynix listing); 408 (per alternate datasheet listing - see note) |
| Package Type | β | 144-pin FineLine BGA (FBGA) |
| Logic Family | β | CMOS |
| Core Technology | β | 0.22 Β΅m CMOS, SRAM-based configuration |
| Supply Voltage (Core) | β | 1.71 V to 1.89 V (1.8 V nominal) |
| Configuration Interface | β | IEEE 1149.1 JTAG + serial configuration (external EPCx required) |