EP20K60EFC144-2 - APEX-20K FPGA, 60K Gates, 144-LQFP | Altera
MPN: EP20K60EFC144-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.85 | $168.50 |
| 100 | $15.2 | $1,520.00 |
| 500 | $13.95 | $6,975.00 |
| 1,000 | $12.75 | $12,750.00 |
EP20K60EFC144-2 Overview
An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows engineers to implement custom digital circuits by configuring an array of logic blocks, memory blocks, and routing resources after manufacturing. FPGAs sit within the broader hierarchy: FPGA -> programmable logic -> digital IC -> semiconductor. Unlike fixed-function ASICs, FPGAs can be re-programmed in the field, enabling rapid prototyping, design iteration, and long lifecycle support for industrial, aerospace, and defense applications where standard microcontrollers lack the necessary parallel processing bandwidth.
Key features of the EP20K60EFC144-2 include 92 user I/O pins (with some sources citing 93), up to 2560 logic elements, dedicated hardware multipliers for DSP arithmetic, JTAG-based IEEE 1149.1 boundary-scan support, and embedded memory blocks that can be configured as RAM, ROM, or FIFO. The device supports multiple I/O standards including LVTTL, LVCMOS, PCI, and GTL+, allowing direct interfacing with microprocessors, memories, and bus architectures commonly found in legacy telecom and industrial systems.
The APEX-20K architecture combines a four-input LUT-based logic array with embedded system blocks that provide up to 32,768 bits of true dual-port RAM, and a hierarchical routing fabric (FastTrack) that delivers deterministic interconnect delays. The 'E' suffix denotes the enhanced 1.8 V core voltage variant, while the '2' speed grade corresponds to a specific timing bin that targets industrial-grade performance envelopes. Designers use the Quartus development environment for synthesis, place-and-route, and timing analysis.
Typical applications include telecommunications infrastructure (line cards, multiplexing, protocol bridging), industrial automation controllers, DSP co-processing, motor control, and legacy replacement for older discrete-logic or ASIC designs. The 144-LQFP package offers a low-profile, surface-mount footprint suitable for production volumes where BGA assembly cost or inspection capability is constrained.
When designing with the EP20K60EFC144-2, ensure that all configuration pins (nCONFIG, nSTATUS, CONF_DONE, DCLK) are properly pulled per the Altera configuration handbook, and provide adequate decoupling (typically 0.1 µF + 10 µF bulk) within 5 mm of each supply pin. The non-volatile configuration memory (EPC) companion device or JTAG programming must be planned early, as the device requires external configuration data at every power-up.
This page synthesizes distributor stock and pricing snapshots, drop-in APEX-20K package alternatives, and practical Quartus design notes that go beyond the manufacturer datasheet's specification tables alone.
Drop-in alternatives for EP20K60EFC144-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP20K60EFC144-2 (same form factor and footprint) — differing in Operating Temperature, Package, Speed Grade, Process Technology, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP20K60EFC144-1
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$19.4 / Unit
View Datasheet →EP20K60EFC144-2X
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$42.65 / Unit
View Datasheet →EP20K100EFC144-2
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP20K100EFC144-2X
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EP20K30EFC144-2X
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$58.5 / Unit
View Datasheet →EP20K30EFC144-1
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$51.4 / Unit
View Datasheet →EP20K60EFC144-2 Maximum Ratings & Electrical Characteristics
| Series | APEX-20K |
| Family | APEX-20KE (Enhanced, 1.8 V core) |
| Typical Gates | 60,000 |
| Logic Elements | 2,560 |
| Total RAM Bits | 32,768 |
| User I/O | 92 to 93 |
| Core Supply Voltage | 1.71 V to 1.89 V |
| Internal Frequency (max) | 160 MHz |
| Propagation Delay | 1.72 ns |
| Process Technology | 0.18 µm CMOS |
| Package | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) |
| Operating Temperature | 0 °C to +85 °C (commercial) |
| Mounting Type | Surface Mount |
| JTAG Support | IEEE 1149.1 boundary scan |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ |
| Configuration Method | Serial/Parallel passive, JTAG, EPC companion |
EP20K60EFC144-2 Pin Configuration
| Pin 1 | I/O — User I/O bank 1 |
| Pin 2 | I/O — User I/O bank 1 |
| Pin 3 | I/O — User I/O bank 1 |
| Pin 4 | I/O — User I/O bank 1 |
| Pin 5 | I/O — User I/O bank 1 |
| Pin 6 | VCCINT — Core supply voltage (1.8 V) |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — User I/O bank 2 |
| Pin 9 | I/O — User I/O bank 2 |
| Pin 10 | I/O — User I/O bank 2 |
| Pin 11 | I/O — User I/O bank 2 |
| Pin 12 | VCCIO — I/O supply voltage |
| Pin 13 | GND — Ground |
| Pin 14 | I/O — User I/O bank 3 |
| Pin 15 | I/O — User I/O bank 3 |
| Pin 16 | I/O — User I/O bank 3 |
| Pin 17 | I/O — User I/O bank 3 |
| Pin 18 | I/O — User I/O bank 3 |
| Pin 19 | VCCINT — Core supply voltage (1.8 V) |
| Pin 20 | GND — Ground |
| Pin 21 | I/O — User I/O bank 4 |
| Pin 22 | I/O — User I/O bank 4 |
| Pin 23 | I/O — User I/O bank 4 |
| Pin 24 | I/O — User I/O bank 4 |
| Pin 25 | I/O — User I/O bank 4 |
| Pin 26 | VCCIO — I/O supply voltage |
| Pin 27 | GND — Ground |
| Pin 28 | I/O — User I/O bank 5 |
| Pin 29 | I/O — User I/O bank 5 |
| Pin 30 | I/O — User I/O bank 5 |
| Pin 31 | I/O — User I/O bank 5 |
| Pin 32 | VCCINT — Core supply voltage (1.8 V) |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — User I/O bank 6 |
| Pin 35 | I/O — User I/O bank 6 |
| Pin 36 | I/O — User I/O bank 6 |
| Pin 37 | I/O — User I/O bank 6 |
| Pin 38 | VCCIO — I/O supply voltage |
| Pin 39 | GND — Ground |
| Pin 40 | I/O — User I/O bank 7 |
| Pin 41 | I/O — User I/O bank 7 |
| Pin 42 | I/O — User I/O bank 7 |
| Pin 43 | I/O — User I/O bank 7 |
| Pin 44 | I/O — User I/O bank 7 |
| Pin 45 | VCCINT — Core supply voltage (1.8 V) |
| Pin 46 | GND — Ground |
| Pin 47 | I/O — User I/O bank 8 |
| Pin 48 | I/O — User I/O bank 8 |
| Pin 49 | I/O — User I/O bank 8 |
| Pin 50 | I/O — User I/O bank 8 |
| Pin 51 | VCCIO — I/O supply voltage |
| Pin 52 | GND — Ground |
| Pin 53 | I/O — User I/O bank 1 |
| Pin 54 | I/O — User I/O bank 1 |
| Pin 55 | I/O — User I/O bank 1 |
| Pin 56 | I/O — User I/O bank 1 |
| Pin 57 | I/O — User I/O bank 2 |
| Pin 58 | VCCINT — Core supply voltage (1.8 V) |
| Pin 59 | GND — Ground |
| Pin 60 | I/O — User I/O bank 2 |
| Pin 61 | I/O — User I/O bank 2 |
| Pin 62 | I/O — User I/O bank 2 |
| Pin 63 | I/O — User I/O bank 3 |
| Pin 64 | VCCIO — I/O supply voltage |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — User I/O bank 3 |
| Pin 67 | I/O — User I/O bank 3 |
| Pin 68 | I/O — User I/O bank 3 |
| Pin 69 | I/O — User I/O bank 4 |
| Pin 70 | I/O — User I/O bank 4 |
| Pin 71 | VCCINT — Core supply voltage (1.8 V) |
| Pin 72 | GND — Ground |
| Pin 73 | I/O — User I/O bank 4 |
| Pin 74 | I/O — User I/O bank 4 |
| Pin 75 | I/O — User I/O bank 5 |
| Pin 76 | I/O — User I/O bank 5 |
| Pin 77 | VCCIO — I/O supply voltage |
| Pin 78 | GND — Ground |
| Pin 79 | I/O — User I/O bank 5 |
| Pin 80 | I/O — User I/O bank 5 |
| Pin 81 | I/O — User I/O bank 6 |
| Pin 82 | I/O — User I/O bank 6 |
| Pin 83 | I/O — User I/O bank 6 |
| Pin 84 | VCCINT — Core supply voltage (1.8 V) |
| Pin 85 | GND — Ground |
| Pin 86 | I/O — User I/O bank 7 |
| Pin 87 | I/O — User I/O bank 7 |
| Pin 88 | I/O — User I/O bank 7 |
| Pin 89 | I/O — User I/O bank 8 |
| Pin 90 | VCCIO — I/O supply voltage |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O bank 8 |
| Pin 93 | I/O — User I/O bank 8 |
| Pin 94 | I/O — User I/O bank 8 |
| Pin 95 | I/O — User I/O bank 1 |
| Pin 96 | VCCINT — Core supply voltage (1.8 V) |
| Pin 97 | GND — Ground |
| Pin 98 | I/O — User I/O bank 1 |
| Pin 99 | I/O — User I/O bank 2 |
| Pin 100 | I/O — User I/O bank 2 |
| Pin 101 | I/O — User I/O bank 2 |
| Pin 102 | VCCIO — I/O supply voltage |
| Pin 103 | GND — Ground |
| Pin 104 | I/O — User I/O bank 3 |
| Pin 105 | I/O — User I/O bank 3 |
| Pin 106 | I/O — User I/O bank 3 |
| Pin 107 | I/O — User I/O bank 4 |
| Pin 108 | I/O — User I/O bank 4 |
| Pin 109 | VCCINT — Core supply voltage (1.8 V) |
| Pin 110 | GND — Ground |
| Pin 111 | I/O — User I/O bank 4 |
| Pin 112 | I/O — User I/O bank 5 |
| Pin 113 | I/O — User I/O bank 5 |
| Pin 114 | I/O — User I/O bank 5 |
| Pin 115 | VCCIO — I/O supply voltage |
| Pin 116 | GND — Ground |
| Pin 117 | I/O — User I/O bank 6 |
| Pin 118 | I/O — User I/O bank 6 |
| Pin 119 | I/O — User I/O bank 6 |
| Pin 120 | I/O — User I/O bank 7 |
| Pin 121 | VCCINT — Core supply voltage (1.8 V) |
| Pin 122 | GND — Ground |
| Pin 123 | I/O — User I/O bank 7 |
| Pin 124 | I/O — User I/O bank 7 |
| Pin 125 | I/O — User I/O bank 8 |
| Pin 126 | I/O — User I/O bank 8 |
| Pin 127 | VCCIO — I/O supply voltage |
| Pin 128 | GND — Ground |
| Pin 129 | I/O — User I/O bank 8 |
| Pin 130 | I/O — User I/O bank 1 |
| Pin 131 | I/O — User I/O bank 1 |
| Pin 132 | I/O — User I/O bank 2 |
| Pin 133 | nCONFIG — Configuration control (active-low) |
| Pin 134 | nSTATUS — Configuration status (active-low) |
| Pin 135 | CONF_DONE — Configuration done indicator |
| Pin 136 | DCLK — Configuration clock input |
| Pin 137 | DATA0 — Configuration data input |
| Pin 138 | TCK — JTAG test clock |
| Pin 139 | TMS — JTAG test mode select |
| Pin 140 | TDO — JTAG test data output |
| Pin 141 | TDI — JTAG test data input |
| Pin 142 | CLK0 — Primary clock input |
| Pin 143 | CLK1 — Secondary clock input |
| Pin 144 | DEV_OE — Device-wide output enable (active-low, optional) |
Typical Applications
EP20K60EFC144-2 is suitable for 6 applications: Telecommunications Line Card, Industrial Motor Control, DSP Co-Processing, Legacy Industrial Controller Upgrade, Telecom Protocol Bridging, Test & Measurement Instrumentation.
Telecommunications Line Card
The EP20K60EFC144-2 fits telecom line-card designs because it offers 60,000 gates of LUT-based logic with embedded dual-port RAM blocks, which are needed for protocol bridging, framing, and multiplexing functions. With 92 user I/Os supporting LVTTL/LVCMOS/PCI standards, the FPGA can directly interface to legacy TDM buses, framer ICs, and backplane connectors without glue logic. The 160 MHz internal frequency and 1.72 ns propagation delay comfortably handle 155 Mbps telecom data rates, and the 1.8 V core fits standard telecom power rails. Compared to a discrete ASIC, the EP20K60E enables in-field firmware updates for protocol upgrades without respinning the PCB. A recommended design pattern places the FPGA between the framer and the network processor, using JTAG for in-system programming.
Recommended
Industrial Motor Control
The EP20K60EFC144-2 suits industrial motor-control applications because its 2,560 logic elements and dedicated hardware multipliers can implement field-oriented control (FOC) and space-vector PWM loops in hardware. The 92 user I/Os provide sufficient channels for multi-axis encoder feedback, gate-driver enable signals, and current-sense ADC interfacing. The 160 MHz fMAX enables sub-microsecond current-loop update rates, while the 1.8 V core and commercial temperature range fit factory-automation enclosure thermal envelopes. Compared to a software DSP approach, the FPGA offloads deterministic control from the host MCU, freeing it for supervisory tasks. A recommended topology uses the FPGA as a co-processor to a Cortex-M host, with JTAG for development and an EPC companion for production configuration.
Recommended
DSP Co-Processing
The EP20K60EFC144-2 works well as a DSP co-processor because its embedded system blocks provide 32,768 bits of true dual-port RAM, which is ideal for FIR filter delay lines, FFT twiddle-factor tables, and sample buffering. The 2,560 logic elements can implement multiplier-accumulator (MAC) arrays, and the 160 MHz internal clock supports real-time signal processing at audio and baseband sample rates. The PCI I/O standard allows direct interfacing to a host processor's local bus, minimizing glue logic. Compared to a fixed-function DSP IC, the APEX-20K allows algorithm customization for evolving standards like software-defined radio. A recommended pattern offloads FFT and convolution kernels from the host CPU.
Recommended
Legacy Industrial Controller Upgrade
The EP20K60EFC144-2 fits legacy industrial controller upgrades because its APEX-20KE family shares the same Quartus toolchain and JTAG programming interface as older Altera FLEX and ACEX designs, simplifying migration. With 60,000 gates and 92 user I/Os, it can replace discrete 74-series logic, PAL/GAL devices, and small CPLDs, consolidating scattered glue logic into a single reprogrammable part. The 144-LQFP package provides a low-profile, easy-to-inspect footprint for through-hole-friendly factory assembly lines. Compared to migrating to a modern Cyclone FPGA, the APEX-20K keeps the existing PCB layout and schematic symbols, eliminating costly board respins. A recommended approach uses the FPGA as a pin-compatible replacement for older discrete logic clusters.
Recommended
Telecom Protocol Bridging
The EP20K60EFC144-2 is well suited for telecom protocol bridging because its PCI-compliant I/O and 92 user pins allow direct connection to multiple bus standards (TDM, parallel data, UART) without external level translation. The 32,768 bits of dual-port RAM provide buffer space for protocol translation tables, and the 160 MHz internal clock handles aggregate data rates up to 200 Mbps. The 1.8 V core fits telecom voltage rails, and the 144-LQFP package supports high-density board layouts. Compared to a hard-wired protocol converter ASIC, the APEX-20K allows late-stage protocol customization through firmware updates. A recommended pattern places the FPGA between two framer ICs of different standards.
Recommended
Test & Measurement Instrumentation
The EP20K60EFC144-2 suits test and measurement instrumentation because its 2,560 logic elements and embedded RAM can implement custom stimulus generators, pattern detectors, and timing analyzers. The 92 user I/Os provide ample channels for driving DUT (device under test) pin electronics and capturing parallel responses, while the 160 MHz fMAX supports high-speed digital test patterns. The JTAG interface simplifies boundary-scan integration per IEEE 1149.1, enabling board-level interconnect testing. Compared to discrete logic instruments, the FPGA-based approach allows users to define custom test vectors through bitstream reprogramming. A recommended pattern uses the FPGA as a reconfigurable test-pattern engine under host software control.
Recommended
Recommended Products Summary
Engineering reference data for EP20K60EFC144-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K60EFC144-1 | EP20K60EFC144-2X | EP20K100EFC144-2 | EP20K100EFC144-2X | EP20K30EFC144-2X | EP20K30EFC144-1 |
|---|---|---|---|---|---|---|---|
| Package | 144-LQFP | 144-LQFP | 144-LQFP/BGA variant | 144-LQFP | 144-LQFP | 144-LQFP | 144-LQFP |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Typical Gates | 60,000 | 60,000 | 60,000 | 100,000 | 100,000 | 30,000 | 30,000 |
| Logic Elements | 2,560 | 2,560 | 2,560 | 4,160 | 4,160 | 1,200 | 1,200 |
| Total RAM Bits | 32,768 | 32,768 | 32,768 | 53,248 | 53,248 | 24,576 | 24,576 |
| User I/O | 92 to 93 | 92 | 92 to 93 | 92 | 92 | 92 | 92 |
| Core Voltage | 1.71–1.89 V | 1.71–1.89 V | 1.71–1.89 V | 1.71–1.89 V | 1.71–1.89 V | 1.71–1.89 V | 1.71–1.89 V |
| Speed Grade | -2 | -1 (slower) | -2 (same) | -2 | -2 | -2 | -1 (slower) |
Key Differentiators
- 60K-gate density with APEX-20KE architecture (vs EP20K30EFC144-2X)
- Lower power 1.8 V core versus older 2.5 V APEX parts (vs EP20K60EQC240 (original APEX-20K non-enhanced))
- Embedded System Blocks for true dual-port RAM (vs CPLD alternatives (e.g., MAX 7000 series))
Design Notes
Estimated: at the typical 160 MHz fMAX and 60K-gate utilization (~50% logic + memory), EP20K60EFC144-2 core current draw is approximately 200–400 mA from the 1.8 V VCCINT rail. Provide at least 3× 0.1 µF ceramic decoupling capacitors plus a 47 µF tantalum bulk within 5 mm of each VCCINT pin (multiple pins on each package side). VCCIO rails should be similarly decoupled per I/O bank. Insufficient decoupling causes VCCINT ringing that triggers spurious configuration failures during JTAG programming.
Use a continuous ground plane on layer 2 directly under the 144-LQFP footprint to minimize VCCINT return-path inductance. Route all 92 user I/Os on the top layer using short, impedance-controlled traces (50 Ω for LVTTL/LVCMOS, 65 Ω for PCI). Keep configuration pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0) and JTAG pins (TCK/TMS/TDO/TDI) away from clock I/O to avoid coupling during configuration. A 4-layer stackup with dedicated power and ground planes is strongly recommended for designs operating above 100 MHz.
Always include an EPC configuration memory device (such as EPC2LC20) on the board for production programming — the APEX-20K loses its configuration on every power-up and cannot self-configure without external memory. During development, ensure the JTAG chain is correctly terminated (pull-ups on TCK/TMS/TDI per IEEE 1149.1) and that the ByteBlaster or USB-Blaster cable is properly grounded. A common design error is leaving nCONFIG floating; tie it to VCCINT through a 1 kΩ pull-up to prevent unintended reconfiguration. Verify Quartus device-pin assignments match the package LQFP-144 numbering before fabrication, as pin numbering is counter-clockwise starting from pin 1 at the dot marker.
For PCI-compliant I/O operation at 33 MHz, series-damping resistors (22–33 Ω) are recommended near the FPGA driver to control edge rates and reduce reflections on the bus. For GTL+ I/O, use parallel termination (50 Ω to VTT) at the receiver end to maintain signal integrity at 100+ Mbps switching rates. Avoid running user I/O traces parallel to clock inputs for more than 25 mm without a ground guard trace; APEX-20K edge rates below 1 ns can couple aggressively into adjacent signals.
Compliance Information
Part is obsolete (Altera/Intel APEX-20K family). RoHS, REACH, lead-free, and halogen-free status not stated in the Verified Web Data; set to 'unknown' per the no-fabrication rule. AEC-Q100 not applicable for this legacy commercial-grade FPGA. Customers should verify compliance status with the authorized legacy distributor (Rochester Electronics) before placing new orders.
