EP20K60EFC144-2 vs EP20K60EFC144-1 Comparison
Detailed side-by-side comparison of EP20K60EFC144-2 by Altera and EP20K60EFC144-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K60EFC144-2 | EP20K60EFC144-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.75 | $19.40 |
| Series | APEX-20K | APEX 20K |
| Family | APEX-20KE (Enhanced, 1.8 V core) | β |
| Typical Gates | 60,000 | 60,000 |
| Logic Elements | 2,560 | β |
| Total RAM Bits | 32,768 | β |
| User I/O | 92 to 93 | β |
| Core Supply Voltage | 1.71 V to 1.89 V | 1.8 V |
| Internal Frequency (max) | 160 MHz | β |
| Propagation Delay | 1.72 ns | 1.72 ns |
| Process Technology | 0.18 Β΅m CMOS | β |
| Package | 144-LQFP (also referenced as 144-FBGA 13x13 in some sources) | 144-FBGA (Fine-pitch BGA) |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) | 0 C to 85 C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| JTAG Support | IEEE 1149.1 boundary scan | β |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL+ | β |
| Configuration Method | Serial/Parallel passive, JTAG, EPC companion | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Device Family | β | APEX 20KE |
| Logic Family | β | CMOS |
| Maximum System Gates | β | 256,000 |
| Macrocells | β | 256 |
| Maximum User I/Os | β | 93 (per datasheet; 196 max in 144-FBGA family datasheet) |
| Embedded Memory | β | 32,768 bits (2560 RAM blocks) |
| Maximum Internal Frequency | β | 160 MHz |
| Speed Grade | β | -1 |
| Package Pin Count | β | 144 balls |
| Programming Interface | β | JTAG / ByteBlaster / Altera Programming Unit |