EP2A15F672C9N vs EP2A15F672C9 Comparison
Detailed side-by-side comparison of EP2A15F672C9N by Intel and EP2A15F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A15F672C9N | EP2A15F672C9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $155.00 | $175.00 |
| Logic Family | APEX II (CMOS) | APEX II (CMOS) |
| Series | Altera APEX II (EP2A) | β |
| Logic Elements / Cells | 16,640 | β |
| Equivalent Gates | 600,000 | β |
| Maximum User I/O Pins | 492 | β |
| Propagation Delay | 1.94 ns | 1.94 ns |
| Internal Operating Frequency (max) | 379 MHz | β |
| Technology Process | 0.15 Β΅m all-layer copper CMOS, up to 8 metal layers | β |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Package | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine BGA) | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Operating Temperature | 0Β°C to +85Β°C (commercial grade) | 0 Β°C to 85 Β°C (commercial) |
| Mounting Type | Surface Mount | β |
| MSL Level | 3 (per FC-FBGA moisture sensitivity, typical) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | β |
| I/O Speed Grade | Up to 1 Gbps (LVDS) | β |
| Embedded Memory | Embedded dual-port RAM blocks | ESB dual-port RAM / FIFO |
| Special Blocks | CAM (Content-Addressable Memory), dedicated multipliers, PLLs | β |
| Speed Grade | C9 (fastest commercial grade in the APEX II speed-grade system) | β |
| Usable Gates | β | 600 K |
| Logic Elements | β | 16640 |
| Macrocells | β | 1664 |
| Maximum User I/Os | β | 492 |
| Process Technology | β | 0.15 Β΅m all-layer copper (up to 8 metal layers) |
| I/O Supply Voltage | β | 3.3 V |
| Maximum Internal Frequency | β | 379 MHz |
| High-Speed I/O Support | β | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Configuration Interface | β | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | β | On-chip PLLs for clock synthesis and deskew |
| Compliance | β | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |