EP2A15F672C9 - 16,640-Cell APEX II FPGA, 672-FBGA | Intel / Altera
MPN: EP2A15F672C9 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $232.5 | $23,250.00 |
| 500 | $198.75 | $99,375.00 |
| 1,000 | $175 | $175,000.00 |
EP2A15F672C9 Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), embedded memory blocks, and programmable interconnect, all controlled by a user-defined SRAM configuration bitstream. Within the broader taxonomy of programmable logic, APEX II sits between traditional CPLDs and modern high-density FPGAs: it provides LUT-based logic plus embedded dual-port RAM, and supports multiplier blocks for DSP workloads. As a member of the power-management and digital-logic ecosystem, an FPGA like the EP2A15F672C9 typically replaces discrete glue logic, custom ASICs, and DSP processors in communications, video, and embedded compute systems.
Key features of the EP2A15F672C9 include 16640 logic elements (LEs), 1664 macrocells, a maximum internal operating frequency in the 300-400 MHz range, 0.15 µm CMOS process technology, and a core supply of 1.5 V. The device also provides dedicated True-LVDS / LVPECL / PCML differential I/O channels rated up to 1 Gbps, embedded system blocks (ESBs) for dual-port RAM and FIFO, JTAG-based IEEE 1149.1 boundary-scan test support, and on-chip PLLs for clock multiplication and deskew. The FineLine BGA-672 substrate enables dense board-level routing while preserving signal integrity on high-speed parallel buses.
Architecturally, the EP2A15F672C9 relies on a row/column-based embedded array, with each Logic Array Block (LAB) containing 10 LEs, fast carry chains, and cascade paths. ESBs implement dual-port RAM with byte enables, while the APEX II MultiCore interconnect links logic, memory, and I/O elements via continuous, fast, and direct routing resources. The process and the dedicated I/O circuitry together enable 1 Gbps True-LVDS operation - a leading-edge specification for the early-2000s APEX II generation.
Typical applications include high-speed parallel data acquisition systems, telecom backplane bridges, video broadcast and image-processing pipelines, network routers and switches with custom protocol offload, and military/aerospace signal processing. The combination of 492 user I/Os, 1 Gbps LVDS channels, and embedded multipliers makes the EP2A15F672C9 particularly well suited to multi-channel serializers / deserializers (SERDES) and protocol-conversion designs.
When designing with this part, careful attention must be paid to signal-integrity on the 1 Gbps LVDS pairs, decoupled supply islands for the 1.5 V core and 3.3 V I/O rails, and thermal management of the 27 x 27 mm BGA under high toggle rates. Configuration via the passive or active serial scheme should be validated against the target JTAG/AS port topology before board bring-up.
This page synthesizes distributor pricing snapshots, same-brand drop-in alternatives from the APEX II family, and practical design notes that complement (rather than duplicate) the original Altera APEX II Programmable Logic Device Family datasheet (DS-APEXII-3.0, August 2002).
Drop-in alternatives for EP2A15F672C9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2A15F672C9 (same form factor and footprint) — differing in Package, Operating Temperature, Process Technology, Family, Embedded Memory.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2A15F672C7
✅ Drop-In✓ In Stock
$98 / Unit
View Datasheet →EP2A15F672C8
✅ Drop-In📋 Reference alternative (not in catalog)
EP2A15F672I8
✅ Drop-In✓ In Stock
$680 / Unit
View Datasheet →EP2A15F672I9
✅ Drop-In📋 Reference alternative (not in catalog)
EP2A15B724C9
✅ Drop-In✓ In Stock
$268.5 / Unit
View Datasheet →EP2A15F672C9 Maximum Ratings & Electrical Characteristics
| Logic Family | APEX II (CMOS) |
| Usable Gates | 600 K |
| Logic Elements | 16640 |
| Macrocells | 1664 |
| Maximum User I/Os | 492 |
| Package | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) |
| Core Supply Voltage | 1.5 V |
| I/O Supply Voltage | 3.3 V |
| Maximum Internal Frequency | 379 MHz |
| Propagation Delay | 1.94 ns |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Embedded Memory | ESB dual-port RAM / FIFO |
| Operating Temperature | 0 °C to 85 °C (commercial) |
| Configuration Interface | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | On-chip PLLs for clock synthesis and deskew |
EP2A15F672C9 672-ball fc-fbga (27 x 27 mm, 1 mm pitch, fineline) Pin Configuration Guide
Pin configuration for EP2A15F672C9 (672-ball fc-fbga (27 x 27 mm, 1 mm pitch, fineline) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2A15F672C9.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2A15F672C9 is suitable for 6 applications: High-Speed Parallel Data Acquisition, Telecom Backplane Bridge / Protocol Converter, Broadcast Video Processing / Image Pipeline, Industrial Control / Custom Protocol Offload, Network Router / Switch Line-Card Glue Logic, Legacy Avionics & Defense Sustainment.
High-Speed Parallel Data Acquisition
The EP2A15F672C9 is well suited to multi-channel parallel data-acquisition front ends because its 1 Gbps True-LVDS / LVPECL / PCML I/O support enables direct interface to high-speed ADCs without external serializers. According to the APEX II datasheet (DS-APEXII-3.0), the device's 492 user I/Os can fan out to dozens of 12-14 bit ADCs sampled at 100-200 MSPS, while the 16 640 logic elements and embedded multipliers provide on-chip channel calibration and digital down-conversion. The 1.5 V core / 3.3 V I/O split simplifies mixed-voltage ADC integration. Compared to a discrete FIFO + DSP implementation, EP2A15F672C9 reduces board area, BOM count, and latency.
Recommended
Telecom Backplane Bridge / Protocol Converter
The EP2A15F672C9's 1 Gbps HyperTransport and LVPECL support, combined with 492 I/Os and 16 640 LEs, make it a strong fit for telecom backplane bridging and protocol conversion (e.g. SPI 4.2 to XAUI, or custom TDM-to-Ethernet bridges). The APEX II datasheet documents dedicated high-speed I/O channels capable of 1 Gbps each, supporting aggregated multi-gigabit serial bandwidth per device. The 1.5 V core keeps power consumption manageable in densely populated line cards. Trade-off: APEX II is obsolete, so design teams should weigh this against modern Stratix/Cyclone families if a board respin is feasible.
Recommended
Broadcast Video Processing / Image Pipeline
The EP2A15F672C9 finds application in SD/HD broadcast video processors, where its 492 I/Os enable multi-format input aggregation (composite, SDI, DVI), 16640 LEs provide real-time scaling, de-interlacing, and color-space conversion, and the 1 Gbps LVDS channels drive downstream SDI serializers. According to the APEX II datasheet, embedded system blocks (ESBs) provide dual-port RAM and FIFO for line and frame buffers, eliminating external memory in lower-resolution pipelines. The 27 x 27 mm BGA allows dense PCB placement typical of broadcast processing boards. Power dissipation is dominated by LVDS I/O switching and must be budgeted thermally.
Recommended
Industrial Control / Custom Protocol Offload
For industrial controllers requiring custom fieldbus or proprietary protocols, the EP2A15F672C9's 492 I/Os, 1664 macrocells of combinational + sequential logic, and on-chip PLLs provide a flexible platform for hardware-accelerated protocol engines. The 0-85 °C commercial grade suits cabinet-mounted industrial controllers; for harsher environments, the EP2A15F672I8 / I9 industrial variants share the same footprint. According to the APEX II datasheet, the embedded multipliers support custom DSP filtering on sensor inputs. Trade-off vs modern Cyclone IV: lower power but EOL on new production, so industrial designers should plan lifecycle strategy.
Recommended
Network Router / Switch Line-Card Glue Logic
The EP2A15F672C9 historically served as glue logic and custom packet-processing fabric in mid-density router / switch line cards, where its 492 I/Os map to multiple PHY MACs and its 16 640 LEs run header parsing and queue management. The 1.5 V core aligns with mid-2000s line-card power trees, and 1 Gbps True-LVDS links connect to switch-fabric ASICs. According to the APEX II datasheet, on-chip PLLs generate the multi-frequency clocks required by Ethernet and SONET PHYs. Modern designs should migrate to Cyclone V or Stratix V for active support, but the EP2A15F672C9 remains useful for sustaining legacy installed base.
Recommended
Legacy Avionics & Defense Sustainment
Because the APEX II family was qualified to MIL-STD-883B flows for industrial and military temperature grades, the EP2A15F672C9 -9 speed grade continues to be sourced for sustainment of legacy avionics and defense platforms. The 16 640 LEs deliver mid-density logic for radar signal processing, sensor I/O aggregation, and MIL-STD-1553 / ARINC 429 bridges. The 27 x 27 mm BGA package supports ruggedized board variants. According to the APEX II datasheet, the same silicon is available in industrial-temperature bins (EP2A15F672I8/I9) for non-flight applications. Designers must verify lot screening and counterfeit mitigation on obsolete stock.
Recommended
Recommended Products Summary
Engineering reference data for EP2A15F672C9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2A15F672C7 | EP2A15F672C8 | EP2A15F672I8 | EP2A15F672I9 | EP2A15B724C9 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 672-ball FC-FBGA (27x27 mm, 1 mm pitch) | 672-ball FC-FBGA (27x27 mm, 1 mm pitch) - same | 672-ball FC-FBGA (27x27 mm, 1 mm pitch) - same | 672-ball FC-FBGA (27x27 mm, 1 mm pitch) - same | 672-ball FC-FBGA (27x27 mm, 1 mm pitch) - same | 724-ball FineLine BGA - different footprint |
| Logic Elements | 16640 | 16640 | 16640 | 16640 | 16640 | 16640 |
| Speed Grade | -9 (fast) | -7 (slow) | -8 (mid) | -8 industrial | -9 industrial (fast) | -9 |
| Temperature Grade | Commercial 0 to 85 °C | Commercial 0 to 85 °C | Commercial 0 to 85 °C | Industrial -40 to 100 °C | Industrial -40 to 100 °C | Commercial 0 to 85 °C |
| Process Technology | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper | 0.15 µm all-layer copper |
| Core Supply | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V | 1.5 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest speed grade in the EP2A15F672 family (vs EP2A15F672C7)
- Industrial temperature range option in same footprint (vs EP2A15F672I8)
- Highest-density APEX II device in 672-ball BGA (vs EP2A15F672C8)
Design Notes
Estimated: The EP2A15F672C9 requires a 1.5 V VCCINT rail and a 3.3 V VCCIO rail; place 100 nF ceramic decoupling caps within 5 mm of every supply pin pair, plus 10 µF bulk capacitors per power island. According to the APEX II datasheet, inrush during configuration can be significant - sequence the 1.5 V core before the 3.3 V I/O if your system supports power-good signals, and use soft-start controllers on the 1.5 V regulator to avoid hot-plug glitches on the FBGA's large decoupling network.
For 1 Gbps True-LVDS / LVPECL channels, follow the APEX II datasheet's controlled-impedance routing rules: 100 Ω differential microstrip or stripline, length-matched to within 5 ps across each LVDS pair, and length-matched across parallel lanes (e.g. within 50 ps). Series-termination resistors are typically NOT required for True-LVDS outputs from APEX II, but place 100 Ω across each receiver pair within 5 mm of the receiver input. Avoid routing LVDS lanes parallel to 3.3 V single-ended buses to minimize crosstalk.
Estimated: At full toggle rate with most I/O active, the 27 x 27 mm FineLine BGA can dissipate 3-6 W depending on utilization. According to the APEX II datasheet, the FC-FBGA package requires a thermal pad connection to an internal ground / power plane. Provide at least 4 thermal vias (0.3 mm drill, 0.5 mm pitch) directly under the BGA thermal balls to conduct heat into the inner-plane copper; for sustained >3 W dissipation, mount a heatsink or forced-air cooling. Verify junction temperature using the Altera PowerPlay early-power estimator before final layout.
Common pitfalls with EP2A15F672C9 designs: (1) confusing the C7/C8/C9 speed-grade bins - timing closure at -7 will fail at the same Fmax budget as -9; (2) assuming EP2A15F672C9 has the same JTAG ID as EP2A15B724C9 - read the BSDL file before board bring-up; (3) forgetting that the APEX II configuration bitstream is incompatible with Cyclone / Stratix - a Quartus II version that supports APEX II (e.g. Quartus II 13.0 or earlier) is required; (4) counterfeit risk on obsolete stock - insist on lot-trace documentation and X-ray inspection when sourcing from independent distributors.
PCB layout recommendations: use 1.0 mm pitch BGA fanout with via-in-pad or dog-bone micro-via, microstrip on the top layer for 50 Ω SE / 100 Ω diff controlled impedance, and continuous reference planes on layers 2 and 4. Route 1 Gbps LVDS lanes on the top microstrip with ground reference plane on layer 2; route slower 3.3 V LVCMOS signals on inner stripline with power/ground reference. According to the APEX II datasheet, the FC-FBGA package is flip-chip, so the BGA thermal balls must be soldered to inner-plane copper for ground return and thermal dissipation.
Compliance Information
RoHS / REACH / lead-free status for EP2A15F672C9 was not explicitly stated in the verified web data; APEX II datasheet (DS-APEXII-3.0) predates RoHS harmonization (August 2002), so older factory stock may not be RoHS-compliant. Confirm with distributor or manufacturer before placing orders for RoHS-restricted regions. AEC-Q100 is not applicable (FPGA is not an automotive-qualified part per the datasheet).
